DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER
WITH 1.5A LDO SUPPORT LOW IQ
Buck Controller (VDDQ)
• High Input Voltages Range from 3V to 28V Input
• Provide Adjustable Output Voltage from 0.75V to
5.5V +1% Accuracy over Temperature
• Integrated MOSFET Drivers and Bootstrap Forward
• Low Quiescent Current (200µA)
• Excellent Line and Load Transient Responses
• PFM Mode for Increased Light Load Efficiency
• Constant On-Time Controller Scheme
- Switching Frequency Compensation for PWM
- Adjustable Switching Frequency from 400kHz to
550kHz in PWM Mode with DC Output Current
• S3 and S5 Pins Control The Device in S0, S3 or S4/
• Power Good Monitoring
• 70% Under-Voltage Protection (UVP)
• 125% Over-Voltage Protection (OVP)
• Adjustable Current-Limit Protection
- Using Sense Low-Side MOSFET’s RDS(ON)
• TQFN-20 3mmx3mm Thin package
• Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
• Sourcing or Sinking Current up to 1.5A
• Fast Transient Response for Output Voltage
• Output Ceramic Capacitors Support at least 10µF
• VTT and VTTREF Track at Half the VDDQSNS by
• +20mV Accuracy for VTT and VTTREF
• Independent Over-Current Limit (OCL)
• Thermal Shutdown Protection
The APW8868C integrates a synchronous buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It offers the lowest total
solution cost in system where space is at a premium.
The APW8868C provides excellent transient response
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW8868C
provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. On TQFN-20
Package, the Forced PWM Mode works nearly at con-
stant frequency for low-noise requirements.
The APW8868C is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on.
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
The output voltage of LDO tracks the voltage at VREF pin.
An internal resistor divider is used to provide a half volt-
age of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capaci-
tance for stability and fast transient response. The S3
and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
Copyright © ANPEC Electronics Corp.
Rev. A.3 - Feb., 2019