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ANPEC

APW8869B Datasheet Preview

APW8869B Datasheet

DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER

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APW8869B
DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER
WITH 1.5A LDO SUPPORT LOW IQ
Features
Buck Controller (VDDQ)
High Input Voltages Range from 6V to 21V Input
Power
Provide Adjustable Output Voltage from 0.9V to
2V +1%Accuracy over Temperature
Integrated MOSFET Drivers and Bootstrap Forward
P-CH MOSFET
Low Quiescent Current (200µA)
Excellent Line and Load Transient Responses
PFM Mode for Increased Light Load Efficiency
Constant On-Time Controller Scheme
- Switching Frequency Compensation for PWM
Mode
- Adjustable Switching Frequency from 400kHz to
550kHz in PWM Mode with DC Output Current
S3 and S5 Pins Control The Device in S0, S3 or S4/
S5 State
Power Good Monitoring
70% Under-Voltage Protection (UVP)
125% Over-Voltage Protection (OVP)
Adjustable Current-Limit Protection
- Using Sense Low-Side MOSFETs RDS(ON)
TQFN-20 3mmx3mm Thin package
Lead Free Available (RoHS Compliant)
+1.5A LDO Section (VTT)
Sourcing or Sinking Current up to 1.5A
Fast Transient Response for Output Voltage
Output Ceramic Capacitors Support at least 10µF
MLCC
VTT and VTTREF Track at Half the VDDQSNS by
internal divider
+20mV Accuracy for VTT and VTTREF
Independent Over-Current Limit (OCL)
Thermal Shutdown Protection
General Description
The APW8869B integrates a synchronous buck PWM con-
troller to generate VDDQ, a sourcing and sinking LDO
linear regulator to generate VTT. It offers the lowest total
solution cost in system where space is at a premium.
The APW8869B provides excellent transient response
and accurate DC voltage output in either PFM or PWM
Mode. In Pulse Frequency Mode (PFM), the APW8869B
provides very high efficiency over light to heavy loads with
loading-modulated switching frequencies. On TQFN-20
Package, the Forced PWM Mode works nearly at con-
stant frequency for low-noise requirements.
The APW8869B is equipped with accurate current-limit,
output under-voltage, and output over-voltage protections.
A Power-On- Reset function monitors the voltage on VCC
prevents wrong operation during power on.
The LDO is designed to provide a regulated voltage with
bi-directional output current for DDR-SDRAM termination.
The device integrates two power transistors to source or
sink current up to 1.5A. It also incorporates current-limit
and thermal shutdown protection.
The output voltage of LDO tracks the voltage at VREF pin.
An internal resistor divider is used to provide a half volt-
age of VREF for VTTREF and VTT Voltage. The VTT output
voltage is only requiring 20µF of ceramic output capaci-
tance for stability and fast transient response. The S3
and S5 pins provide the sleep state for VTT (S3 state)
and suspend state (S4/S5 state) for device, when S5 and
S3 are both pulled low the device provides the soft-off for
VTT and VTTREF.
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and
advise customers to obtain the latest version of relevant information to verify before placing orders.
Copyright © ANPEC Electronics Corp.
1
Rev. A.2 - Apr., 2019
www.anpec.com.tw




ANPEC

APW8869B Datasheet Preview

APW8869B Datasheet

DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER

No Preview Available !

APW8869B
Simplified Application Circuit Applications
VIN
6V~21V
VDDQ
Q1
LOUT
Q2
5V
VCC CS
RCS
DDR2, and DDR3/DDR3L Memory Power Supplies
SSTL-2 SSTL-18 and HSTL Termination
PWM
DDR
LDO
VTT
VDDQ/2
S3 S5
Ordering and Marking Information
APW8869B
Lead Free Code
Handling Code
Temperature Range
Package Code
Package Code
QB : TQFN3x3-20
Operating
I : -40 to
8A5m°bCient
Temperature
Range
Handling Code
TR : Tape & Reel
Lead Free Code
G : Halogen and Lead Free Device
APW8869B QB :
APW
8869B
XXXXX
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which
are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020D for
MSL classification at lead-free peak reflow temperature. ANPEC defines Greento mean lead-free (RoHS compliant) and halogen
free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by
weight).
Pin Configuration
20 19 18 17 16
VTTGND 1
VTTSNS 2
GND 3
VTTREF 4
VDDQSNS 5
21
PGND
15 LGATE
14 PGND
13 CS
12 VCC
11 VCC
6 7 8 9 10
= Thermal Pad (connected to GND plane for better heat dissipation)
Copyright © ANPEC Electronics Corp.
2
Rev. A.2 - Apr., 2019
www.anpec.com.tw



Part Number APW8869B
Description DDR2 AND DDR3/DDR3L SYNCHRONOUS BUCK CONTROLLER
Maker ANPEC
Total Page 3 Pages
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