AX68004 Datasheet | ASIX

Features Single chip microcontroller with 2-port (AX68002) /4-Port (AX68004) USB KVM Switch CPU for Application 8-bit pipelined RISC, single cycle per instruction operating up to 96MHz and 100% software patible with standard 8051/80390 Supports power management unit with deep sleep mode, programmable watchdog timer, three 16-bit timer/counters, and millisecond timer Supports CPU Debugger for connecting to In-Circuit Emulation (ICE) adaptor Supports DMA Controller (7 DMA channels) and memory arbiter for fast data movement during network protocol stack processing and peripheral munications 1 external interrupt sources with 2 priority levels Program/Data and Flash Memory On-chip 8KB SRAM for CPU program code mirroring Supports In-System Programming (ISP) for initial Flash memory programming via UART or ICE adaptor Supports reprogrammable boot code and In-Application Programming (IAP) to update boot code or run-time firmware through USB or UART interface On-chip 32KB data memory for CPU and packet buffering On-chip 128KB Flash memory for CPU program code On-chip 1KB Flash Information Page for Hardware Configuration Supports Page architecture for flash erase Minimum 100,000 flash program/erase cycles Minimum 10 years flash data retention under maximum 20 times pre-cycles USB Interfaces Supports 2/4 multi-addressable Device Controllers and pliant with USB Spec 2.0 Full speed Build-in one USB host controller and one USB root hub that supports four downstream ports and each pliant with USB2.0 Full/Low speed Supports Control, Bulk, Interrupt, and Isochronous transfer types. Support controllable D+ pull-up resistance for upstream ports Support controllable D+/- pull-down resistance for downstream ports Document No: AX6800x/V1.02/05/28/2015 Support Burst mode transfer for BULK data transfer in Device Controller Supports the downstream SOF synchronization with selected upstream port for ISO data transfer automatically Peripheral munication Interfaces 2 UART interface (1...