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AX88195P Datasheet Preview

AX88195P Datasheet

10/100BASE Fast Ethernet MAC Controller

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AX88195P
10/100BASE Fast Ethernet MAC Controller
10/100BASE Local CPU Bus Fast Ethernet MAC Controller
Features
Document No.: AX195-17 / V1.7 / May. 12 ’00
IEEE 802.3u 100BASE-T, TX, and T4 Compatible
Single chip local CPU bus 10/100Mbps Fast
Ethernet MAC Controller
NE2000 register level compatible instruction
Support both 8 bit and 16 bit local CPU interfaces
include MCS-51 series, 80186 series and MC68K
series CPU
Support both 10Mbps and 100Mbps data rate
Support both full-duplex or half-duplex operation
Provides a MII port for both 10/100Mbps operation
Support EEPROM interface to store MAC address
External and internal loop-back capability
Two external 32K*8 Asynchronous SRAMs
required for packet buffer
128-pin LQFP low profile package
25MHz Operation, Dual 5V and 3.3V CMOS
process with 5V I/O tolerance. Or pure 3.3V
operation
*IEEE is a registered trademark of the Institute of Electrical and Electronic
Engineers, Inc.
*All other trademarks and registered trademark are the property of their
respective holders.
Product description
The AX88195 Fast Ethernet Controller is a high performance and highly integrated local CPU bus Ethernet Controller.
The AX88195 supports both 8 bit and 16 bit local CPU interfaces include MCS-51 series, 80x86 series, MC68K series
CPU and ISA bus. The AX88195 implements both 10Mbps and 100Mbps Ethernet function based on IEEE802.3 /
IEEE802.3u LAN standard and supports both 10Mbps/100Mbps media-independent interface (MII) to simplify the
design. Two low cost 32k*8 SRAM is required for packet buffer.
System Block Diagram
AD BUS
BUFFER
SRAM
Addr L
Addr H
Ctl BUS
AX88195
PHY/TxRx
RJ45
Always contact ASIX for possible updates before starting a design.
This data sheet contains new products information. ASIX ELECTRONICS reserves the rights to modify product specification without notice. No liability
is assumed as a result of the use of this product. No rights under any patent accompany the sale of the product.
ASIX ELECTRONICS CORPORATION
First Released Date : Oct/02/1998
2F, NO.13, Industry East Rd. II, Science-based Industrial Park, Hsin-Chu City, Taiwan, R.O.C.
TEL: 886-3-579-9500
FAX: 886-3-579-9558
http://www.asix.com.tw




ASIX

AX88195P Datasheet Preview

AX88195P Datasheet

10/100BASE Fast Ethernet MAC Controller

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AX88195 Local CPU Bus Fast Ethernet MAC Controller
CONTENTS
1.0 INTRODUCTION .............................................................................................................................................. 4
1.1 GENERAL DESCRIPTION:..................................................................................................................................... 4
1.2 AX88195 BLOCK DIAGRAM: .............................................................................................................................. 4
1.3 AX88195 PIN CONNECTION DIAGRAM ............................................................................................................... 5
1.3.1 AX88195 Pin Connection Diagram for ISA Bus Mode................................................................................ 6
1.3.2 AX88195 Pin Connection Diagram for 80x86 Mode................................................................................... 7
1.3.3 AX88195 Pin Connection Diagram for MC68K Mode ................................................................................ 8
1.3.4 AX88195 Pin Connection Diagram for MCS-51 Mode ............................................................................... 9
2.0 SIGNAL DESCRIPTION ................................................................................................................................. 10
2.1 LOCAL CPU BUS INTERFACE SIGNALS GROUP................................................................................................... 10
2.2 MII INTERFACE SIGNALS GROUP........................................................................................................................ 11
2.3 EEPROM SIGNALS GROUP .............................................................................................................................. 12
2.4 SRAM INTERFACE PINS GROUP......................................................................................................................... 12
2.5 MISCELLANEOUS PINS GROUP............................................................................................................................ 12
2.6 POWER ON CONFIGURATION SETUP SIGNALS CROSS REFERENCE TABLE ................................................................ 13
3.0 MEMORY AND I/O MAPPING...................................................................................................................... 14
3.1 EEPROM MEMORY MAPPING.......................................................................................................................... 14
3.2 I/O MAPPING................................................................................................................................................... 14
3.3 SRAM MEMORY MAPPING .............................................................................................................................. 14
4.0 REGISTERS OPERATION ............................................................................................................................. 15
4.1 COMMAND REGISTER (CR) OFFSET 00H (READ/WRITE)................................................................................... 17
4.2 INTERRUPT STATUS REGISTER (ISR) OFFSET 07H (READ/WRITE) ..................................................................... 17
4.3 INTERRUPT MASK REGISTER (IMR) OFFSET 0FH (WRITE) ................................................................................. 18
4.4 DATA CONFIGURATION REGISTER (DCR) OFFSET 0EH (WRITE) ....................................................................... 18
4.5 TRANSMIT CONFIGURATION REGISTER (TCR) OFFSET 0DH (WRITE) ................................................................ 18
4.6 TRANSMIT STATUS REGISTER (TSR) OFFSET 04H (READ) ................................................................................ 19
4.7 RECEIVE CONFIGURATION (RCR) OFFSET 0CH (WRITE) .................................................................................. 19
4.8 RECEIVE STATUS REGISTER (RSR) OFFSET 0CH (READ) .................................................................................. 19
4.9 INTER-FRAME GAP (IFG) OFFSET 16H (READ/WRITE) ...................................................................................... 20
4.10 INTER-FRAME GAP SEGMENT 1(IFGS1) OFFSET 12H (READ/WRITE) ............................................................... 20
4.11 INTER-FRAME GAP SEGMENT 2(IFGS2) OFFSET 13H (READ/WRITE) ............................................................... 20
4.12 MII/EEPROM MANAGEMENT REGISTER (MEMR) OFFSET 14H (READ/WRITE) .............................................. 20
4.13 TEST REGISTER (TR) OFFSET 15H (WRITE) ................................................................................................... 20
5.0 CPU I/O READ AND WRITE FUNCTIONS .................................................................................................. 21
5.1 ISA BUS TYPE ACCESS FUNCTIONS. ................................................................................................................... 21
5.2 80186 CPU BUS TYPE ACCESS FUNCTIONS......................................................................................................... 21
5.3 MC68K CPU BUS TYPE ACCESS FUNCTIONS...................................................................................................... 22
5.3 MCS-51 CPU BUS TYPE ACCESS FUNCTIONS. .................................................................................................... 22
6.0 ELECTRICAL SPECIFICATION AND TIMINGS........................................................................................ 23
6.1 ABSOLUTE MAXIMUM RATINGS ........................................................................................................................ 23
6.2 GENERAL OPERATION CONDITIONS................................................................................................................... 23
6.3 DC CHARACTERISTICS..................................................................................................................................... 23
6.4 A.C. TIMING CHARACTERISTICS....................................................................................................................... 24
6.4.1 XTAL / CLOCK........................................................................................................................................ 24
6.4.2 Reset Timing ............................................................................................................................................ 24
6.4.3 ISA Bus Access Timing............................................................................................................................. 25
6.4.4 80186 Type I/O Access Timing ................................................................................................................. 26
2 ASIX ELECTRONICS CORPORATION


Part Number AX88195P
Description 10/100BASE Fast Ethernet MAC Controller
Maker ASIX
Total Page 30 Pages
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