AX88796C Datasheet | ASIX

AX88796C Low-Power SPI or Non-PCI Ethernet Controller Features Document No.: AX88796C/V1.14/04/15/11 High-performance non-PCI local bus Supports 8/16-bit SRAM-like host interface (US Patent Approval), easily interfaced to most mon embedded MCUs; or 8/16-bit local CPU interface including MCS-51 series, Renesas series CPUs Supports Slave-DMA to minimize CPU overhead and burst mode read & write access for frame reception & transmission on SRAM-like interface for high performance applications Supports variable voltage I/O (1.8/2.5/3.3V) and programmable driving strength (8/16m A) Interrupt pin with programmable timer High-performance SPI slave interface Supports SPI slave interface for CPU with SPI master. The SPI slave interface supports SPI timing mode 0 and 3, up to 40MHz of SPI CLK, variable voltage I/O and programmable driving strength Supports optional Ready signal as flow control for SPI packet RX/TX Single-chip Fast Ethernet MAC/PHY controller Embeds 14KB SRAM for packet buffers Supports IPv4/IPv6 packet Checksum Offload Engine to reduce CPU loading, including IPv4 IP/TCP/UDP/ICMP/IGMP & IPv6 TCP/UDP/ICM Pv6 checksum generation & check Supports VLAN match filter Integrates IEEE 802.3/802.3u standards patible 10BASE-T/100BASE-TX (twisted pair copper mode) Fast Ethernet MAC/PHY transceiver in one single-chip Supports twisted pair crossover detection and correction (HP Auto-MDIX) Supports full duplex operation with IEEE 802.3x flow control and half duplex operation with back-pressure flow control Supports auto-polling function Supports 10/100Mbps N-way Auto-negotiation operation Advanced Power Management Features Supports dynamic power management to reduce power dissipation during idle or light traffic period Supports very low power Wake-On-LAN (WOL) mode when the system enters sleep mode and waits for network event to awake it up. The wakeup events supported are network link state change, receipt of a Magic Packet or a pre-programmed Microsoft Wakeup...