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Features
• High-density, High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device – 128 Macrocells – 5.0 ns Pin-to-pin Propagation Delay – Registered Operation up to 333 MHz – Enhanced Routing Resources – Optimized for 3.3V Operation – On-chip Voltage Regulator – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.5V, 1.8V, 2.5V, 3.3V – SSTL2 and SSTL3 I/O Standards
• In-System Programming (ISP) Supported – ISP Using IEEE 1532 (JTAG) Interface – IEEE 1149.