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ATF1516ASL - High-performance EE-based CPLD

Download the ATF1516ASL datasheet PDF. This datasheet also covers the ATF1516AS variant, as both devices belong to the same high-performance ee-based cpld family and are provided as variant models within a single manufacturer datasheet.

Key Features

  • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device.
  • 256 Macrocells.
  • 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell.
  • 160, 192, 208 pins.
  • 10 ns Maximum Pin-to-pin Delay.
  • Registered Operation Up To 100 MHz.
  • Enhanced Routing Resources.
  • Flexible Logic Macrocell.
  • D/T/Latch Configurable Flip-flops.
  • Global and Individual Register Control Signals.
  • Glob.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ATF1516AS-ATMEL.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
ATF1516AE (ATF15xxAE) 2nd Generation EE Complex Programmable Logic Devices ATMEL Corporation
ATF1516SE EEPROM ATMEL Corporation
ATF1516SL EEPROM ATMEL Corporation
ATF1500A High-performance EPLD ATMEL Corporation
ATF1502BE High Speed CPLD ATMEL Corporation

Other Datasheets by Atmel (now Microchip Technology)

Part Number Description
ATF1516AS High-performance EE-based CPLD
ATF1500ABV High-performance EE PLD
ATF1500AL High-performance EPLD
ATF1502AS High-performance EEPROM
ATF1502ASL High-performance EEPROM

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Features • High-density, High-performance, Electrically-erasable Complex Programmable Logic Device – 256 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 160, 192, 208 pins – 10 ns Maximum Pin-to-pin Delay – Registered Operation Up To 100 MHz – Enhanced Routing Resources • Flexible Logic Macrocell – D/T/Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate – Programmable Output Open Collector Option – Maximum Logic Utilization by Burying a Register within a COM Output • Advanced Power Management Features – Automatic 3 mA Standby for “L” Version (Maximum) – Pin-controlled 4 mA Standby Mode (Typical) – Programmable Pin-keeper Inputs and I/Os – Reduced-power Feature pe