45DB011 Key Features
- Single 2.7V
- 3.6V Supply
- Serial Interface Architecture
- Page Program Operation
- Single Cycle Reprogram (Erase and Program)
- 512 Pages (264 Bytes/Page) Main Memory Optional Page and Block Erase Operations One 264-Byte SRAM Data Buffer Internal P
- 7 ms Typical 120 µs Typical Page to Buffer Transfer Time Low-Power Dissipation
- 4 mA Active Read Current Typical
- 2 µA CMOS Standby Current Typical 13 MHz Max Clock Frequency Hardware Data Protection Feature Serial Peripheral Interfac
- Modes 0 and 3 CMOS and TTL patible Inputs and Outputs mercial and Industrial Temperature Ranges