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Atmel Electronic Components Datasheet

45DB041 Datasheet

AT45DB041

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AT45DB041
Features
Single 2.7V - 3.6V Supply
Serial Interface Architecture
Page Program Operation
Single Cycle Reprogram (Erase and Program)
2048 Pages (264 Bytes/Page) Main Memory
Two 264-Byte Data Buffers - Allows Receiving of Data while Reprogramming of
Non-Volatile Memory
Internal Program and Control Timer
Fast Page Program Time - 7 ms Typical
120 ms Typical Page to Buffer Transfer Time
Low Power Dissipation
4 mA Active Read Current Typical
8 mA CMOS Standby Current Typical
5 MHz Max Clock Frequency
Hardware Data Protection Feature
Serial Peripheral Interface (SPI) Compatible – Modes 0 and 3
CMOS and TTL Compatible Inputs and Outputs
Commercial and Industrial Temperature Ranges
Description
The AT45DB041 is a 2.7-volt only, serial interface Flash memory suitable for in-sys-
tem reprogramming. Its 4,325,376 bits of memory are organized as 2048 pages of
264-bytes each. In addition to the main memory, the AT45DB041 also contains two
data buffers of 264-bytes each. The buffers allow receiving of data while a page in the
main memory is being reprogrammed. Unlike conventional Flash memories that are
accessed randomly with multiple address lines and a parallel interface, the DataFlash
uses a serial interface to sequentially access its data. The simple serial interface facil-
itates hardware layout, increases system reliability, minimizes switching noise, and
Pin Configurations
(continued)
PLCC
Pin Name
Function
CS
SCK
SI
SO
WP
Chip Select
Serial Clock
Serial Input
Serial Output
Hardware Page Write
Protect Pin
SCK 5
SI 6
SO 7
NC 8
NC 9
NC 10
NC 11
NC 12
NC 13
29 WP
28 RESET
27 RDY/BUSY
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
RESET
RDY/BUSY
Chip Reset
Ready/Busy
Note: PLCC package pin 16
is DON’T CONNECT.
RDY/BUSY 1
RESET 2
WP 3
NC 4
NC 5
VCC 6
GND 7
NC 8
NC 9
NC 10
CS 11
SCK 12
SI 13
SO 14
TSOP Top View
Type 1
28 NC
27 NC
26 NC
25 NC
24 NC
23 NC
22 NC
21 NC
20 NC
19 NC
18 NC
17 NC
16 NC
15 NC
SOIC
VSS
1
NC
2
NC
3
CS
4
SCK
5
SI
6
SO
7
NC
8
NC
9
NC
10
NC
11
NC
12
NC
13
NC
14
28
VCC
27
NC
26
NC
25
WP
24
RESET
23
RDY/BUSY
22
NC
21
NC
20
NC
19
NC
18
NC
17
NC
16
NC
15
NC
4-Megabit
2.7-Volt Only
Serial
DataFlash
AT45DB041
0669A-A
1


Atmel Electronic Components Datasheet

45DB041 Datasheet

AT45DB041

No Preview Available !

reduces package size and active pin count. The device is
optimized for use in many commercial and industrial appli-
cations where high density, low pin count, low voltage, and
low power are essential. Typical applications for the
DataFlash are digital voice storage, image storage, and
data storage. The device operates at clock frequencies up
to 5 Mhz with a typical active read current consumption of
4 mA.
To allow for simple in-system reprogrammability, the
AT45DB041 does not require high input voltages for pro-
gramming. The device operates from a single power sup-
ply, 2.7V to 3.6V, for both the program and read opera-
tions. The AT45DB041 is enabled through the chip select
pin (CS) and accessed via a three-wire interface consisting
of the Serial Input (SI), Serial Output (SO), and the Serial
Clock (SCK).
All programming cycles are self-timed, and no separate
erase cycle is required before programming.
Block Diagram
WP
FLASH MEMORY ARRAY
PAGE (264 BYTES)
BUFFER 1 (264 BYTES)
BUFFER 2 (264 BYTES)
SCK
CS
RESET
VCC
GND
RDY/BUSY
I/O INTERFACE
SI
SO
Device Operation
The device operation is controlled by instructions from the
host processor. The list of instructions and their associated
opcodes are contained in Tables 1 and 2. A valid instruc-
tion starts with the falling edge of CS followed by the appro-
priate 8-bit opcode and the desired buffer or main memory
address location. While the CS pin is low, toggling the SCK
pin controls the loading of the opcode and the desired
buffer or main memory address location through the SI
(serial input) pin. All instructions, addresses, and data are
transferred with the most significant bit (MSB) first.
Read
By specifying the appropriate opcode, data can be read
from the main memory or from either one of the two data
buffers.
MAIN MEMORY PAGE READ: A main memory read allows
the user to read data directly from any one of the 2048
pages in the main memory, bypassing both of the data buff-
ers and leaving the contents of the buffers unchanged. To
start a page read, the 8-bit opcode, 52H, is followed by 24
address bits and 32 don’t care bits. In the AT45DB041, the
first four address bits are reserved for larger density
devices (see Notes on page 7), the next 11 address bits
(PA10-PA0) specify the page address, and the next nine
address bits (BA8-BA0) specify the starting byte address
within the page. The 32 don’t care bits which follow the 24
address bits are sent to initialize the read operation. Fol-
lowing the 32 don’t care bits, additional pulses on SCK
result in serial data being output on the SO (serial output)
pin. The CS pin must remain low during the loading of the
opcode, the address bits, and the reading of data. When
the end of a page in main memory is reached during a main
memory page read, the device will continue reading at the
beginning of the same page. A low to high transition on the
CS pin will terminate the read operation and tri-state the
SO pin.
BUFFER READ: Data can be read from either one of the
two buffers, using different opcodes to specify which buffer
to read from. An opcode of 54H is used to read data from
buffer 1, and an opcode of 56H is used to read data from
2
AT45DB041


Part Number 45DB041
Description AT45DB041
Maker ATMEL Corporation
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45DB041 Datasheet PDF






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