AT17C010 Datasheet | Atmel

Features - E2 Programmable 524,288 x 1 and 1,048,576 x 1 bit Serial Memories Designed To Store Configuration Programs For Field Programmable Gate Arrays (FPGA) - Simple Interface to SRAM FPGAs - patible With Atmel AT6000, AT40K FPGAs, Altera EPF8K, EPF10K, - - - - - - - - EPF6K FPGAs, ORCA FPGAs, Xilinx XC3000, XC4000, XC5200 FPGAs, Motorola MPA1000 FPGAs Cascadable To Support Additional Configurations or Future Higher-density Arrays Low-power CMOS EEPROM Process Programmable Reset Polarity Available In PLCC Package (Pin patable across Product Family) In-System Programmable Via 2-Wire Bus Emulation of 24CXX Serial EPROMs Available in 3.3V ± 10% LV and 5V Versions System Friendly READY Pin Description The AT17C512/010 and AT17LV512/010 (high-density AT17 Series) FPGA Configuration EEPROMs (Configurators) provide an easy-to-use, cost-effective configuration memory for Field Programmable Gate Arrays. The high-density AT17 Series is packaged in the popular 20-pin PLCC. The high-density AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The high-density AT17 Series organization supplies enough memory to configure one or multiple smaller FPGAs. The user can select the polarity of the reset function by programming one EEPROM byte. The devices also support a write protection mode and a system friendly READY pin, which signifies a “good” power level to the device and can be used to ensure reliable system power-up. The high-density AT17 Series can be programmed with industry-standard programmers, and the Atmel ATDH2200 Programming board. FPGA Configuration E2PROM Memory 512K and 1M AT17C512 AT17LV512 AT17C010 AT17LV010 Pin Configurations 20-Pin PLCC N C D A T A N C V C C N C CLK WP1 RESET/OE WP2 CE 4 5 6 7 8 9 19 18 17 16 15 14 13 NC SER_EN NC R E A DY CEO Rev. 0944A-A- 12/97 Controlling The High-Density AT17 Series Serial EEPROMs Most connections between the FPGA device...