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Atmel Electronic Components Datasheet

AT17F040 Datasheet

FPGA Configuration Flash Memory

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AT17F040 and AT17F080
FPGA Configuration Flash Memory
DATASHEET
Features
Programmable 4,194,304 x 1 and 8,388,608 x 1-bit Serial Memories Designed
to Store Configuration Programs for Field Programmable Gate Arrays (FPGAs)
3.3V Output Capability
5.0V Tolerant I/O Pins
Program Support using the Atmel ATDH2200E System, ATDH2225 ISP cable,
or Third-party Programmers
In-System Programmable (ISP) via 2-wire Bus
Simple Interface to SRAM FPGAs
Compatible with Atmel AT40K and AT94K Devices, Altera® FLEX®, APEX
Devices, Lucent® ORCA® FPGAs, Xilinx® XC3000, XC4000, XC5200,
Spartan®, Virtex® FPGAs, and Motorola® MPA1000 FPGAs
Cascadable Read-back to Support Additional Configurations or Higher-density
Arrays
Low-power CMOS FLASH Process
Available in 6mm x 6mm x 1mm 8-pad LAP (Pin-compatible with 8-lead
SOIC/VOIC Packages) and 20-lead PLCC Packages
Emulation of the Atmel AT24C Serial EEPROMs
Low-power Standby Mode
Single Device Capable of Holding 4-Bitstream Files Allowing Simple System
Reconfiguration
Fast Serial Download Speeds up to 33MHz
Endurance: 100,000 Write Cycles Typical
Green (Pb/Halide-free/RoHS Compliant) Package Options
Description
The Atmel® AT17F Series of In-System Programmable Configuration PROMs
(Configurators) provide an easy-to-use, cost-effective configuration memory
solution for FPGAs. The AT17F Series devices are packaged in the 8-pad LAP
and 20-lead PLCC packages (Table 1-1). The AT17F Series Configurators use a
simple serial-access procedure to configure one or more FPGA devices.
The AT17F Series Configurators can be programmed with industry-standard
programmers, the Atmel ATDH2200E Programming Kit or the Atmel ATDH2225
ISP Cable.
Table 1. AT17F Series Packages
Package
8-pad LAP
20-lead PLCC
AT17F040
Yes
Yes
AT17F080
Yes
Yes
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015


Atmel Electronic Components Datasheet

AT17F040 Datasheet

FPGA Configuration Flash Memory

No Preview Available !

1. Pin Configurations
Table 1-1. Pin Descriptions
DATA(1)
CLK(1)
PAGE_EN(2)
PAGESEL[1:0](2)
RESET/OE(1)
CE(1)
GND
CEO
A2(1)
READY
SER_EN (1)
VCC
Three-state DATA Output for Configuration. Open-collector bi-directional pin for programming.
Clock Input. Used to increment the internal address and bit counter for reading and programming.
Enable Page Download Mode Input. When PAGE_EN is high the configuration download address
space is partitioned into four equal pages. This gives users the ability to easily store and retrieve
multiple configuration bitstreams from a single configuration device. This input works in conjunction
with the PAGESEL inputs. PAGE_EN must be remain low if paging is not desired. When SER_EN is
Low (ISP mode) this pin has no effect.
Page Select Input. Used to determine which of the four memory pages are targeted during a serial
configuration download. The address space for each of the pages is shown in Table 1-2. When
SER_EN is Low (ISP mode) these pins have no effect.
Output Enable (Active High) and RESET (Active Low) when SER_EN is High. A Low level on
RESET/OE resets both the address and bit counters. A High level (with CE Low) enables the data
output driver.
Chip Enable Input (Active Low). A Low level (with OE High) allows CLK to increment the address
counter and enables the data output driver. A High level on CE disables both the address and bit
counters and forces the device into a low-power standby mode. Note that this pin will not
enable/disable the device in the 2-wire Serial Programming mode (SER_EN Low).
Ground. A 0.2μF decoupling capacitor between VCC and GND is recommended.
Chip Enable Output (when SER_EN is High). This output goes Low when the internal address
counter has reached its maximum value. If the PAGE_EN input is set High, the maximum value is the
highest address in the selected partition. The PAGESEL[1:0] inputs are used to make the four
partition selections. If the PAGE_EN input is set Low, the device is not partitioned and the address
maximum value is the highest address in the device (Table 1-2). In a daisy chain of AT17F Series
devices, the CEO pin of one device must be connected to the CE input of the next device in the chain.
It will stay Low as long as CE is Low and OE is High. It will then follow CE until OE goes Low;
thereafter, CEO will stay High until the entire EEPROM is read again.
Device Selection Input, (when SER_EN Low). The input is used to enable (or chip select) the
device during programming (i.e., when SER_EN is Low). Refer to the Atmel AT17F Programming
Specification available on the Atmel web site for additional details.
Open Collector Reset State Indicator. Driven Low during power-up reset, released when power-up
is complete. (recommended 4.7kpull-up on this pin if used).
Serial Enable Input. Must remain High during FPGA configuration operations. Bringing SER_EN
Low enables the 2-Wire Serial Programming Mode. For non-ISP applications, SER_EN should be
tied to VCC.
Device Power Supply. +3.3V (±10%)
Notes: 1. Internal 20Kpull-up resistor
2. Internal 30Kpull-up resistor
2 AT17F040/080 [DATASHEET]
Atmel-3039M-CNFG-AT17F040-080-Datasheet_012015


Part Number AT17F040
Description FPGA Configuration Flash Memory
Maker ATMEL Corporation
Total Page 14 Pages
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