AT25F2048 Datasheet | Atmel

Features - - - - - - - - - - - - - - Serial Peripheral Interface (SPI) patible Supports SPI Modes 0 (0,0) and 3 (1,1) 20 MHz Clock Rate Byte Mode and 256-byte Page Mode for Program Operations Sector Architecture: - Four Sectors with 64K Bytes Each - 256 Pages per Sector Product Identification Mode Low-voltage Operation - 2.7 (VCC = 2.7V to 3.6V) Sector Write Protection - Protect 1/4, 1/2 or Entire Array Write Protect (WP) Pin and Write Disable Instructions for both Hardware and Software Data Protection Self-timed Program Cycle (30 µs/Byte Typical) Self-timed Sector Erase Cycle (1 second/Sector Typical) Single Cycle Reprogramming (Erase and Program) for Status Register High Reliability - Endurance: 10,000 Write Cycles Typical 8-lead JEDEC SOIC SPI Serial Memory 2M (262,144 x 8) AT25F2048 Preliminary Description The AT25F2048 provides 2,097,152 bits of serial reprogrammable Flash memory organized as 262,144 words of 8 bits each. The device is optimized for use in many industrial and mercial applications where low-power and low-voltage operation are essential. The AT25F2048 is available in a space-saving 8-lead JEDEC SOIC package. Pin Configurations Pin Name CS SCK SI SO GND VCC WP HOLD Function Chip Select Serial Data Clock Serial Data Input Serial Data Output Ground Power Supply Write Protect Suspends Serial Input CS SO WP GND 8-lead SOIC 1 2 3 4 8 7 6 5 VCC HOLD SCK SI Rev. 2455D- SEEPR- 7/04 The AT25F2048 is enabled through the Chip Select pin (CS) and accessed via a 3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). All write cycles are pletely self-timed. BLOCK WRITE protection for top 1/4, top 1/2 or the entire memory array is enabled by programming the status register. Separate write enable and write disable instructions are provided for additional data protection. Hardware data protection is provided via the WP pin to protect against inadvertent write attempts to the status register. The HOLD pin...