ATLV3 Description
The ATLV Series CMOS gate arrays employ 1.0 µ-drawn, double-level metal, Si-gate, CMOS technology processed in Atmel's U.S.-based, advanced manufacturing facility. The arrays utilize an enhanced channelless architecture which results in greater than 50 percent usable gates. Atmel's flexible design system uses industry design standards and is patible with popular CAD/CAE software and hardware packages.
ATLV3 Applications
- 3.0 Volts and will Operate from 0.7 to 5.5 Volts