AVR32AP Datasheet Text
Feature Summary
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32-bit load/store AVR32B RISC architecture 15 general-purpose 32-bit registers 32-bit Stack Pointer, Program Counter and Link Register reside in register file Fully orthogonal instruction set Pipelined architecture allows one instruction per clock cycle for most instructions Byte, half-word, word and double word memory access Shadowed interrupt context for INT3 and multiple interrupt priority levels Privileged and unprivileged modes enabling efficient and secure Operating Systems Full MMU allows for operating systems with memory protection Instruction and data caches Innovative instruction set together with variable instruction length ensuring industry leading code density DSP extention with saturating arithmetic, and a wide variety of multiply instructions SIMD extention for media applications Dynamic branch prediction and return address stack for fast change-of-flow Powerful On-Chip Debug system Coprocessor interface
32-bit AVR® Microcontroller AVR32 AP Technical Reference Manual
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32001A- AVR32- 06/06
1. Introduction
AVR®32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. In addition, the instruction set architecture has been tuned to allow for a variety of microarchitectures, enabling the AVR32 to be implemented as low-, mid- or high-performance processors.
1.1
The AVR family
The AVR family was launched by Atmel® in 1996 and has had remarkable success in the 8-and 16-bit flash microcontroller market. AVR32 plements the current AVR microcontrollers. Through the AVR32 family, the AVR is extended into a new range of higher performance applications that is...
