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TSEV8388BF Datasheet

ADC 8-bit 1 GSPS

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TSEV8388BF pdf
Features
8-bit Resolution
ADC Gain Adjust
1.5 GHz Full Power Input Bandwidth (-3 dB)
1 GSPS (min) Sampling Rate
SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,
at FS = 1 GSPS, FIN = 20 MHz
SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,
at FS = 1 GSPS, FIN = 500 MHz
SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,
at FS = 1 GSPS, FIN = 1000 MHz (-3 dB FS)
2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS
DNL = 0.3 lsb, INL = 0.7 lsb
Low Bit Error Rate (10-13) at 1 GSPS
Very Low Input Capacitance: 3 pF
500 mVpp Differential or Single-ended Analog Inputs
Differential or Single-ended 50ECL Compatible Clock Inputs
ECL or LVDS/HSTL Output Compatibility
Data Ready Output with Asynchronous Reset
Gray or Binary Selectable Output Data; NRZ Output Mode
Power Consumption: 3.4W at Tj = 70°C Typical
Radiation Tolerance Oriented Design (150 Krad (Si) measured)
Two Package Versions
Evaluation board: TSEV8388B
Demultiplexer TS81102G0: Companion Device Available
ADC 8-bit
1 GSPS
TS8388B
Applications
• Digital Sampling Oscilloscopes
• Satellite Receiver
• Electronic Countermeasures/Electronic Warfare
• Direct RF Down-conversion
Description
The TS8388B is a monolithic 8-bit analog-to-digital converter, designed for digitizing
wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.
The TS8388B uses an innovative architecture,
including an on-chip Sample and Hold (S/H),
and is fabricated with an advanced
high speed bipolar process.
The on-chip S/H has a 1.5 GHz full power
input bandwidth, providing excellent dynamic
performance in undersampling applications
(High IF digitizing).
Rev. 2144C–BDC–04/03
1


Atmel Electronic Components Datasheet

TSEV8388BF Datasheet

ADC 8-bit 1 GSPS

No Preview Available !

TSEV8388BF pdf
Functional
Description
Block Diagram
The following figure shows the simplified block diagram.
Figure 1. Simplified Block Diagram
GAIN
VIN, VINB
MASTER/SLAVE TRACK & HOLD AMPLIFIER
G=2 T/H
G=1 T/H
G=1
RESISTOR
CHAIN
ANALOG
ENCODING
BLOCK
4
4
INTERPOLATION
STAGES
5
CLK, CLKB
CLOCK
BUFFER
DRRB DR, DRB
GORB
REGENERATION
LATCHES
45
ERROR CORRECTION &
DECODE LOGIC
8
OUTPUT LATCHES &
BUFFERS
8
DATA, DATAB OR, ORB
Functional
Description
The TS8388B is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology
featuring a cutoff frequency of 25 GHz.
The TS8388B includes a front-end master/slave Track and Hold stage (S/H), followed by an
analog encoding stage and interpolation circuitry.
Successive banks of latches regenerate the analog residues into logical data before entering
an error correction circuitry and a resynchronization stage followed by 75differential output
buffers.
The TS8388B works in fully differential mode from analog inputs up to digital outputs.
The TS8388B features a full-power input bandwidth of 1.5 GHz.
A control pin GORB is provided to select either Gray or Binary data output format.
A gain control pin is provided in order to adjust the ADC gain.
A Data Ready output asynchronous reset (DRRB) is available on TS8388B.
The TS8388B uses only vertical isolated NPN transistors together with oxide isolated polysili-
con resistors, which allow enhanced radiation tolerance (no performance drift measured at
150 kRad total dose).
2 TS8388B
2144C–BDC–04/03


Part Number TSEV8388BF
Description ADC 8-bit 1 GSPS
Maker ATMEL Corporation
Total Page 30 Pages
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