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Actel

ARINC429 Datasheet Preview

ARINC429 Datasheet

Bus Interface

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ARINC 429 Bus Interface
wwwP.dartaoshdeeut4uc.ctomSummary
Intended Use
• ARINC 429 Transmitter (Tx)
• ARINC 429 Receiver (Rx)
Key Features
• Supports ARINC Specification 429-16
• Configurable up to 16 Rx and 16 Tx Channels
• Programmable FIFO Depth
– Up to 512 Words
• Programmable Interrupt Generation
– Rx and Tx Channels independently
– Up to 64 Words
• Configurable Label Memory Size
– Rx and Tx Channels independently
– Up to 256 Words
• Internal, Wrap-Around Testing
• Software Compatible with Legacy Devices
• Selectable Clock Speed
– 1, 10, 16, or 20 MHz
• Selectable Data Rate on Each Channel
– 12.5 100 kbps
– Optional 50 kbps
• CPU Interface
– Provides Direct CPU Access to Memory
– Simple Interface to Core8051
• Memory
– EDAC Support with RTAX-S Family
• ARINC 429 Bus Interface
– Supports Standard Line Drivers and Receivers
• Available as Integrated Tx and Rx
Supported Families
• Fusion
• ProASIC®3/E
• ProASICPLUS®
• Axcelerator®
• RTAX-S
Core Deliverables
• Evaluation Version
– Compiled RTL Simulation Model, Compliant
with the Actel Libero® Integrated Design
Environment (IDE)
• Netlist Version
– Structural VHDL and Verilog Netlists
• RTL version
– VHDL or Verilog Core Source Code
– Synthesis Scripts
• Verification Testbench – Verilog
• User Testbenches
– Libero IDE Compatible
– VHDL and Verilog
Development System
• Complete ARINC 429 Rx/Tx
• Implementation
– Implemented in an APA600 Device
– Controlled Via an External Terminal Using
Core8051 and RS232 Links
• Includes Line Driver and Receiver Components
Synthesis and Simulation Support
• Directly Supported within the Actel Libero IDE
• Synthesis:
– Synplicity®
– ExemplarTM
– Synopsys®
• Simulation
– Vital-Compliant VHDL Simulators
– OVI-Compliant Verilog Simulators
Verification and Compliance
• Actel-Developed Simulation Testbench
• Core Implemented on the ARINC
Development System
429
September 2006
© 2006 Actel Corporation
v5.0
1




Actel

ARINC429 Datasheet Preview

ARINC429 Datasheet

Bus Interface

No Preview Available !

ARINC 429 Bus Interface
Contents
General Description .................................................... 2
ARINC 429 Overview .................................................. 2
www.dCatoarsehe4e2t94uD.ceovmice Requirements ................................... 3
Memory Requirements ............................................... 4
Core429 Overview ...................................................... 5
Default Mode ............................................................. 5
Functional Description ............................................... 5
Legacy Mode ............................................................... 7
Core Parameters ......................................................... 8
I/O Signal Descriptions ............................................... 8
Default Mode Operation ......................................... 10
Legacy Operation ..................................................... 13
Status Register .......................................................... 15
CPU Interface Timing for Default Mode ................. 16
Clock Requirements .................................................. 17
Core429 Verification ................................................ 17
Testbench .................................................................. 17
Line Drivers ............................................................... 18
Line Receivers ........................................................... 18
Loopback Interface ................................................... 18
Development System ................................................ 18
Ordering Information .............................................. 19
List of Changes ......................................................... 20
Datasheet Categories ............................................... 21
General Description
Core429 provides a complete Transmitter (Tx) and
Receiver (Rx). A typical system implementation using
Core429 is shown in Figure 1.
The core consists of three main blocks: Transmit, Receive,
and CPU Interface (Figure 1). Core429 requires
connection to an external CPU. The CPU interface
configures the transmit and receive control registers and
initializes the label memory. The core interfaces to the
ARINC 429 bus through an external ARINC 429 line driver
and line receiver. A detailed description of the Rx
interface and Tx interface is provided in the "Functional
Description" section on page 5.
External Components
There are two external components required for proper
operation of Core429:
• Standard ARINC 429 line driver
• Standard ARINC 429 line receiver
CPU
Glue
Logic
CPU
Interface
Rx I/F
Tx I/F
RxHi
RxLo
TxHi
TxLo
Figure 1 •
CoreARINC429
Actel FPGA
Typical Core429 System—One Tx and One Rx
ARINC 429 Overview
ARINC 429 is a two-wire, point-to-point data bus that is
application-specific for commercial and transport
aircraft. The connection wires are twisted pairs. Words
are 32 bits in length and most messages consist of a
single data word. The specification defines the electrical
standard and data characteristics and protocols.
ARINC 429 uses a unidirectional data bus standard (Tx
and Rx are on separate ports) known as the Mark 33
Digital Information Transfer System (DITS). Messages are
transmitted at 12.5, 50 (optional), or 100 kbps to other
system elements that are monitoring the bus messages.
The transmitter is always transmitting either 32-bit data
words or the Null state.
The ARINC standard supports High, Low, and Null states
(Figure 2). A minimum of four Null bits should be
transmitted between ARINC words. No more than 20
receivers can be connected to a single bus (wire pair) and
no less than one receiver, though there will normally be
more.
1 2 3 4 5 6 7 8 9 10
High +5
A Null 0
Low –5
High +5
B Null 0
Low –5
1 0 11 01 01 00
32 Bit
Number
"A" Leg
"B" Leg
1 Data
Figure 2 • ARINC Standard
Figure 3 on page 3 shows the bit positions of ARINC
data.
Each ARINC word contains five fields:
• Parity
2 v5.0


Part Number ARINC429
Description Bus Interface
Maker Actel
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