Aeroflex UT8SP2M48
The UT8SP2M48 is a high performance 100,663,296-bit synchronous static random access memory (SSRAM) device that is organized as 2M words of 48 bits. This device is equipped with three chip selects (CS0, CS1, and CS2), a write enable (WE), and an output enable (OE) pin, allowing for significant design flexibility without bus contention. The device supports a four word burst function using (ADV_LD).| Part No. | UT8SP2M48 |
|---|---|
| Datasheet | UT8SP2M48 Download |
| Manufacturer |  Aeroflex |
| Description | 96Megabit Pipelined SSRAM |
| Buy | Stock & Price |
FEATURES
● Synchronous SRAM organized as 2Meg words x 48bit● Continuous Data Transfer (CDT) architecture eliminates wait states between read and write operations
● Supports 40MHz to 133MHz bus operations
● Internally self-timed output buffer control eliminates the need for synchronous output enable
● Registered inputs and outputs for pipelined operation
● Single 2.5V to 3.3V supply
● Clock-to-output time - Clk to Q = 7ns
● Clock Enable (CEN) pin to enable clock and suspend operation
● Synchronous self-timed writes
● Three Chip Enables (CS0, CS1, CS2) for simple depth expansion
● "ZZ" Sleep Mode option for partial power-down
● "SHUTDOWN" Mode option for deep power-down
● Four Word Burst Capability--linear or interleaved
● Operational Environment - Total Dose: 100 krad(Si) - SEL Immune: ≤ 100MeV-cm2/mg - SEU error rate: 1.7x10-6 errors/bit-day
● Package options: - 288-lead CLGA, CCGA, and CBGA
● Standard Microelectronics Drawing (SMD) 5962-15213 - QMLQ and Q+ pending INTRODUCTION All synchronous inputs are registered on the rising edge of the clock provided the Clock Enable (CEN) input is enabled LOW.
