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UT54ACTS138 Datasheet Preview

UT54ACTS138 Datasheet

3-Line to 8-Line Decoders/Demultiplexers

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Standard Products
UT54ACS138/UT54ACTS138
3-Line to 8-Line Decoders/Demultiplexers
Datasheet
November 2010
www.aeroflex.com/logic
FEATURES
‰ 1.2μ CMOS
- Latchup immune
‰ High speed
‰ Low power consumption
‰ Single 5 volt supply
‰ Available QML Q or V processes
‰ Flexible package
- 16-pin DIP
- 16-lead flatpack
‰ UT54ACS138 - SMD 5962-96544
‰ UT54ACTS138 - SMD 5962-96545
DESCRIPTION
The UT54ACS138 and the UT54ACTS138 3-line to 8-line de-
coders/demultiplexers are designed to be used in high-perfor-
mance memory-decoding or data-routing applications requiring
very short propagation delay times.
The conditions at the binary select inputs and the three enable
inputs select one of eight output lines. Two active-low and one
active-high enable inputs reduce the need for external gates of
inverters when expanding. A 24-line decoder can be implement-
ed without external inverters and a 32-line decoder requires only
one inverter. An enable input can be used as a data input for
demultiplexing applications.
PINOUTS
A
B
C
G2A
G2B
G1
Y7
VSS
The devices are characterized over full military temperature
range of -55°C to +125°C.
FUNCTION TABLE
ENABLE INPUTS
G1
G2A
G2B
XXH
LXX
XHX
HL L
HL L
HL L
HL L
HL L
HL L
HL L
HL L
SELECT INPUTS
CBA
XXX
XXX
XXX
LLL
L LH
LHL
LHH
HL L
HLH
HH L
HHH
Y0 Y1
HH
HH
HH
LH
HL
HH
HH
HH
HH
H 1H
HH
Y2
H
H
H
H
H
L
H
H
H
H
H
16-Pin DIP
Top View
A 1 16 VDD
B 2 15 Y0
C 3 14 Y1
G2A 4 13 Y2
G2B 5 12 Y3
G1 6 11 Y4
Y7 7 10 Y5
VSS 8
9 Y6
16-Lead Flatpack
Top View
1 16
2 15
3 14
4 13
5 12
6 11
7 10
89
VDD
Y0
Y1
Y2
Y3
Y4
Y5
Y6
OUTPUT
Y3 Y4 Y5 Y6 Y7
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
HHHHH
L HHHH
H L HHH
HH L HH
HHH L H
HHHH L




Aeroflex Circuit Technology

UT54ACTS138 Datasheet Preview

UT54ACTS138 Datasheet

3-Line to 8-Line Decoders/Demultiplexers

No Preview Available !

LOGIC SYMBOL
A (1)
B (2)
C (3)
G1 (6)
G2A (4)
G2B (5)
BIN/OCT
1
2
4
0
1
2
3
4
&5
EN 6
7
(15) Y0
(14) Y1
(13) Y2
(12) Y3
(11) Y4
(10) Y5
(9) Y6
(7) Y7
A (1)
(2)
B
C (3)
G1 (6)
(4)
G2A
(5)
G2B
Note:
1. Logic symbols in accordance with ANSI/IEEE standard 91-1984 and IEC Publication 617-12.
LOGIC DIAGRAM
DMUX
1
2
G
0---
7
4
&
EN
0
1
2
3
4
5
6
7
(15)
Y0
(14) Y1
(13) Y2
(12)
Y3
(11) Y4
(10) Y5
(9) Y6
(7) Y7
ENABLE
G1 (6)
G2A (4)
G2B (5)
A (1)
SELECT B (2)
C (3)
(15) Y0
(14) Y1
(13) Y2
(12) Y3
(11) Y4
(10) Y5
(9) Y6
(7) Y7
DATA
2


Part Number UT54ACTS138
Description 3-Line to 8-Line Decoders/Demultiplexers
Maker Aeroflex Circuit Technology
Total Page 10 Pages
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