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UT54ACTS138 - 3-Line to 8-Line Decoders/Demultiplexers

Download the UT54ACTS138 datasheet PDF. This datasheet also covers the UT54ACS138 variant, as both devices belong to the same 3-line to 8-line decoders/demultiplexers family and are provided as variant models within a single manufacturer datasheet.

General Description

The UT54ACS138 and the UT54ACTS138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times.

Key Features

  • ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 16-pin DIP - 16-lead flatpack ‰ UT54ACS138 - SMD 5962-96544 ‰ UT54ACTS138 - SMD 5962-96545.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (UT54ACS138-AeroflexCircuitTechnology.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number UT54ACTS138
Manufacturer Aeroflex Circuit Technology
File Size 235.28 KB
Description 3-Line to 8-Line Decoders/Demultiplexers
Datasheet download datasheet UT54ACTS138 Datasheet

Full PDF Text Transcription for UT54ACTS138 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for UT54ACTS138. For precise diagrams, and layout, please refer to the original PDF.

Standard Products UT54ACS138/UT54ACTS138 3-Line to 8-Line Decoders/Demultiplexers Datasheet November 2010 www.aeroflex.com/logic FEATURES ‰ 1.2μ CMOS - Latchup immune ‰ H...

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2010 www.aeroflex.com/logic FEATURES ‰ 1.2μ CMOS - Latchup immune ‰ High speed ‰ Low power consumption ‰ Single 5 volt supply ‰ Available QML Q or V processes ‰ Flexible package - 16-pin DIP - 16-lead flatpack ‰ UT54ACS138 - SMD 5962-96544 ‰ UT54ACTS138 - SMD 5962-96545 DESCRIPTION The UT54ACS138 and the UT54ACTS138 3-line to 8-line decoders/demultiplexers are designed to be used in high-performance memory-decoding or data-routing applications requiring very short propagation delay times. The conditions at the binary select inputs and the three enable inputs select one of eight output lines.