Octal Transparent Latches with Three-State Outputs
8 latches in a single package
Three-state bus-driving true outputs
Full parallel access for loading
- Latchup immune
Low power consumption
Single 5 volt supply
Available QML Q or V processes
- 20-pin DIP
- 20-lead flatpack
UT54ACS373 - SMD 5962-96588
UT54ACTS373 - SMD 5962-96589
The UT54ACS373 and the UT54ACTS373 are 8-bit latches
with three-state outputs designed for driving highly capacitive
or relatively low-impedance loads. The device is suitable for
buffer registers, I/O ports, and bidirectional bus drivers.
The eight latches are transparent D latches. While the enable
(C) is high the Q outputs will follow the data (D) inputs. When
the enable is taken low, the Q outputs will be latched at the levels
that were set up at the D inputs.
An output-control input (OC) places the eight outputs in either
a normal logic state (high or low logic levels) or a high-imped-
ance state. The high-impedance third state and increased drive
provide the capability to drive the bus line in a bus-organized
system without need for interface or pull-up components.
The output control OC does not affect the internal operations of
the latches. Old data can be retained or new data can be entered
while the outputs are off.
The devices are characterized over full military temperature
range of -55°C to +125°C.
OC C nD nQ
L H HH
L H LL
L L X nQ0
H X X Z1
1. Data may be latched internally.
OC 1 20
1Q 2 19
1D 3 18
2D 4 17
2Q 5 16
4D 8 13
4Q 9 12
VSS 10 11
1. Logic symbol in accordance with ANSI/IEEE Std 91-1984 and IEC