TTSV02622 Description
The TTSV02622 can support a 1.24 Gbits/s interface for backplane connections. The 1.24 Gbits/s interface is implemented as dual 622 Mbits/s LVDS links. The HSI macrocell is used for clock/data recovery (CDR) and MUX/deMUX between 77.76 MHz bytewide internal data buses and the 622 Mbits/s external serial links.