Datasheet Details
| Part number | AS4C1G8D3LA |
|---|---|
| Manufacturer | Alliance Semiconductor |
| File Size | 2.14 MB |
| Description | 8Gbit DDR3L SDRAM |
| Datasheet |
 AS4C1G8D3LA Datasheet
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General Description
Clock : CK and CK are differential clock inputs.
Key Features
- - Double-data-rate architecture; two data transfers per clock cycle - The high-speed data transfer is realized by the 8 bits prefetch pipe- lined architecture - Bi-directional differential data strobe (DQS and DQS) is transmitted/ received with data for capturing data at the receiver - DQS is edge-aligned with data for READs; center-aligned with data for WRITEs - Differential clock inputs (CK and CK) - DLL aligns DQ and DQS transitions with CK transitions - Commands entered on each positive CK e.