AS4LC4M4F1 Overview
v.1.0 Restored Alliance Semiconductor AS4LC4M4F1 P. 1 of 14 Copyright © Alliance Semiconductor. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low power and wide operating margins at ponent and system levels.
AS4LC4M4F1 Key Features
- Organization: 4,194,304 words × 4 bits
- High speed
- 50/60 ns RAS access time
- 25/30 ns column address access time
- 12/15 ns CAS access time
- Refresh
- 2048 refresh cycles, 32 ms refresh interval
- RAS-only or CAS-before-RAS refresh or self-refresh
- TTL-patible, three-state I/O
- JEDEC standard package