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AS8C401825 - 3.3V Synchronous SRAMs

Download the AS8C401825 datasheet PDF. This datasheet also covers the AS8C403625 variant, as both devices belong to the same 3.3v synchronous srams family and are provided as variant models within a single manufacturer datasheet.

General Description

TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18.

The AS8C403625/1825 SRAMs contain write, data, address and control registers.

There are no registers in the data output path (flow-through architecture).

Key Features

  •   AS8C403625 AS8C401825.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS8C403625-AllianceSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS8C401825
Manufacturer Alliance Semiconductor
File Size 885.30 KB
Description 3.3V Synchronous SRAMs
Datasheet download datasheet AS8C401825 Datasheet

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Other Datasheets by Alliance Semiconductor

Part Number Description
AS8C401800 3.3V Synchronous SRAMs
AS8C401801 3.3V Synchronous SRAMS
AS8C401801-QC166N 3.3V Synchronous SRAMS
AS8C403600 3.3V Synchronous SRAMs
AS8C403601 3.3V Synchronous SRAMS

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
128K X 36, 256K X 18 3.3V Synchronous SRAMs 3.3V I/O, Flow-Through Outputs Burst Counter, Single Cycle Deselect Features ◆ ◆   AS8C403625 AS8C401825 Description TheAS8C403625/1825 are high-speed SRAMs organized as 128K x 36/256K x 18. The AS8C403625/1825 SRAMs contain write, data, address and control registers. There are no registers in the data output path (flow-through architecture). Internal logic allows the SRAM to generate a self-timed write based upon a decision which can be left until the end of the write cycle. The burst mode feature offers the highest level of performance to the system designer, as the AS8C403625/1825 can provide four cycles of data for a single address presented to the SRAM.