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AS8C801801 - 3.3V Synchronous ZBT SRAMs

Download the AS8C801801 datasheet PDF. This datasheet also covers the AS8C803601 variant, as both devices belong to the same 3.3v synchronous zbt srams family and are provided as variant models within a single manufacturer datasheet.

General Description

The AS8C803601/801801 SRAM utilize IDT's latest high-performance The AS8C803601/801801 are3.3V high-speed 9,437,184 bit CMOS process, andare packaged ina JEDEC Standard 14mm x 20mm 100(9 Megabit) synchronous SRAMS.

They are designed to eliminate dead bus pin thin plastic quad flatpack (TQFP) .

Key Features

  • Pin.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (AS8C803601-AllianceSemiconductor.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number AS8C801801
Manufacturer Alliance Semiconductor
File Size 1.56 MB
Description 3.3V Synchronous ZBT SRAMs
Datasheet download datasheet AS8C801801 Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
256K x 36, 512K x 18 3.3V Synchronous ZBT™ SRAMs ZBT™ Feature 3.3V I/O, Burst Counter Pipelined Outputs ◆ AS8C803601 AS8C801801 Address and control signals are applied to the SRAM during one clock cycle, and two cycles later the associated data cycle occurs, be it read or write. 256K x 36, 512K x 18 memory configurations ◆ The AS8C803601/801801 contain data I/O, address and control signal Supports high performance system speed - 150MHz registers. Output enable is the only asynchronous signal and can be (3.8ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles used to disable the outputsat any given time.