EP1S40 Datasheet Summary
Section I. Stratix Device Family Data Sheet
This section provides designers with the data sheet specifications for Stratix devices. They contain feature definitions of the internal architecture, configuration and JTAG boundary-scan testing information, DC operating conditions, AC timing parameters, a reference to power consumption, and ordering information for Stratix devices. This section contains the following chapters:
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- Chapter 1. Introduction Chapter 2. Stratix Architecture Chapter 3. Configuration & Testing Chapter 4. DC & Switching Characteristics
Revision History
Chapter
1
The table below shows the revision history for Chapter 1 through Chapter 5.
Date/Version
September 2004, v3.1 April 2004, v3.0
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- Changes Made
Updated Table 1- 6 on page 1- 5. Main section page numbers changed on first page. Changed PCI-X to PCI-X 1.0 in “Features
” on page 1- 2. Global change from SignalTap to SignalTap II. The DSP blocks in “Features
” on page 1- 2 provide dedicated implementation of multipliers that are now “faster than 300 MHz.” Updated -5 speed grade device information in Table 1-6. Add -8 speed grade device information. Format changes throughout chapter. m o c . u 4 t e e h s a t a .d w w w
January 2004, v2.2 October 2003, v2.1 July 2003, v2.0
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- Altera Corporation
Section I- 1 Preliminary
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Chapter 5. Reference & Ordering Information
Stratix Device Family Data Sheet
Stratix Device Handbook, Volume 1
Chapter
2
Date/Version
September 2004, v3.1
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