EPM5032, EPM5016 Datasheet - Altera

EPM5032 Programmable Logic

s Programming support with Altera’s Master Programming Unit (MPU) or programming hardware from other manufacturers s Additional design entry and simulation support provided by EDIF, LPM, Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Data I/O, Exemp.

EPM5032 Features

* s Advanced Multiple Array MatriX (MAX) 5000 architecture combining speed and ease-of-use of PAL devices with the density of programmable gate arrays s Complete family of high-performance, erasable CMOS EPROM EPLDs for designs ranging from fast 28-pin address decoders to 100-pin LSI custom periphera

EPM5016_Altera.pdf