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EPM7128E - Programmable Logic

This page provides the datasheet information for the EPM7128E, a member of the EPM7032 Programmable Logic family.

Description

MAX 7000 Programmable Logic Device Family Data Sheet Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar

Features

  • f.
  • High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture.
  • 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices.
  • ISP circuitry compatible with IEEE Std. 1532.
  • Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices.
  • Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more mac.

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Datasheet preview – EPM7128E

Datasheet Details

Part number EPM7128E
Manufacturer Altera
File Size 1.13 MB
Description Programmable Logic
Datasheet download datasheet EPM7128E Datasheet
Additional preview pages of the EPM7128E datasheet.

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Full PDF Text Transcription

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September 2005, ver. 6.7 ® MAX 7000 Programmable Logic Device Family Data Sheet Features... f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) ■ 5-ns pin-to-pin logic delays with up to 175.
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