EPM7160E
Description
MAX 7000 Programmable Logic Device Family Data Sheet - Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar Logic, Mentor Graphics, OrCAD, Synopsys, and VeriBest - Programming support - Altera’s Master Programming Unit (MPU) and programming hardware from third-party manufacturers program all MAX 7000 devices - The BitBlasterTM serial download cable, ByteBlasterMVTM p.
Key Features
- Open-drain output option in MAX 7000S devices
- Programmable macrocell flipflops with individual clear, preset, clock, and clock enable controls
- Programmable power-saving mode for a reduction of over 50% in each macrocell
- Configurable expander product-term distribution, allowing up to 32 product terms per macrocell
- Programmable security bit for protection of proprietary designs
