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EPM7160E - Programmable Logic

Download the EPM7160E datasheet PDF. This datasheet also covers the EPM7032 variant, as both devices belong to the same programmable logic family and are provided as variant models within a single manufacturer datasheet.

Description

MAX 7000 Programmable Logic Device Family Data Sheet Additional design entry and simulation support provided by EDIF 2 0 0 and 3 0 0 netlist files, library of parameterized modules (LPM), Verilog HDL, VHDL, and other interfaces to popular EDA tools from manufacturers such as Cadence, Exemplar

Features

  • f.
  • High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture.
  • 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices.
  • ISP circuitry compatible with IEEE Std. 1532.
  • Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices.
  • Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more mac.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EPM7032-Altera.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EPM7160E
Manufacturer Altera
File Size 1.13 MB
Description Programmable Logic
Datasheet download datasheet EPM7160E Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
EPM7128AE Programmable Logic Device Altera Corporation
EPM7128B (EPM7000B) Programmable Logic Device Altera Corporation
EPM7000B (EPM7000B) Programmable Logic Device Altera Corporation
EPM7032AE Programmable Logic Device Altera Corporation
EPM7032B (EPM7000B) Programmable Logic Device Altera Corporation

Other Datasheets by Altera

Part Number Description
EPM7160EPLD High Performance 160-Macrocell Device
EPM7128E Programmable Logic
EPM7128EPLD Programmable Logic Device
EPM7192E Programmable Logic
EPM7032 Programmable Logic

Full PDF Text Transcription

Click to expand full text
September 2005, ver. 6.7 ® MAX 7000 Programmable Logic Device Family Data Sheet Features... f ■ High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAX® architecture ■ 5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices – ISP circuitry compatible with IEEE Std. 1532 ■ Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices ■ Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells ■ Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2) ■ 5-ns pin-to-pin logic delays with up to 175.
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