Datasheet Summary
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MAX 7000B
®
Programmable Logic Device
Data Sheet
September 2003, ver. 3.4
Features
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High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1)
- Pin-patible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families
- High-density PLDs ranging from 600 to 10,000 usable gates
- 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP)
- Programs through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface with advanced pin-locking capability
- Enhanced ISP...
