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EPM7128B - (EPM7000B) Programmable Logic Device

Download the EPM7128B datasheet PDF. This datasheet also covers the EPM7032B variant, as both devices belong to the same (epm7000b) programmable logic device family and are provided as variant models within a single manufacturer datasheet.

Description

MAX 7000B devices are high-density, high-performance devices based on Altera’s second-generation MAX architecture.

Features

  • High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1).
  • Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families.
  • High-density PLDs ranging from 600 to 10,000 usable gates.
  • 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP).
  • Programs through th.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (EPM7032B_AlteraCorporation.pdf) that lists specifications for multiple related part numbers.

Datasheet Details

Part number EPM7128B
Manufacturer Altera Corporation
File Size 0.96 MB
Description (EPM7000B) Programmable Logic Device
Datasheet download datasheet EPM7128B Datasheet

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Other Datasheets by Altera Corporation

Part Number Description
EPM7128AE Programmable Logic Device
EPM7000B (EPM7000B) Programmable Logic Device
EPM7032AE Programmable Logic Device
EPM7032B (EPM7000B) Programmable Logic Device
EPM7064AE Programmable Logic Device

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
www.DataSheet4U.com MAX 7000B ® Programmable Logic Device Data Sheet September 2003, ver. 3.4 Features... ■ ■ High-performance 2.5-V CMOS EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) – Pin-compatible with the popular 5.0-V MAX 7000S and 3.3-V MAX 7000A device families – High-density PLDs ranging from 600 to 10,000 usable gates – 3.5-ns pin-to-pin logic delays with counter frequencies in excess of 303.0 MHz Advanced 2.5-V in-system programmability (ISP) – Programs through the built-in IEEE Std. 1149.
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