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Analog Devices Semiconductor Electronic Components Datasheet

AD5063 Datasheet

nanoDAC

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Data Sheet
Fully Accurate 16-Bit VOUT nanoDAC
SPI Interface 2.7 V to 5.5 V in an MSOP
AD5063
FEATURES
Single 16-bit DAC, 1 LSB INL
Power-on reset to midscale
Guaranteed monotonic by design
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
10-lead MSOP, low power
Fast settling time of 1 µs maximum (AD5063-1 model)
2.7 V to 5.5 V power supply
Low glitch on power-up
Unbuffered voltage capable of driving 60 kΩ load
SYNC interrupt facility
FUNCTIONAL BLOCK DIAGRAM
VREF
VDD
POWER-ON
RESET
AD5063
BUF
DAC
REGISTER
REF(+)
DAC
RFB
INV
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
AGND
APPLICATIONS
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GENERAL DESCRIPTION
The AD5063, a member of the Analog Device Inc., nanoDAC™
family, is a low power, single 16-bit, unbuffered voltage-output
DAC that operates from a single 2.7 V to 5 V supply. The device
offers a relative accuracy specification of ±1 LSB, and operation
is guaranteed monotonic with a ±1 LSB DNL specification. The
AD5063 comes with on-board resistors in a 10-lead MSOP,
allowing bipolar signals to be generated with an output amplifier.
The device uses a versatile 3-wire serial interface that operates
at clock rates up to 30 MHz and that is compatible with
standard SPI®, QSPI™, MICROWIRE™, and DSP interface
standards. The reference for the AD5063 is supplied from an
external VREF pin. A reference buffer is also provided on-chip.
The device incorporates a power-on reset circuit that ensures
the DAC output powers up to midscale and remains there until
a valid write to the device takes place. The device contains a
power-down feature that reduces the current consumption of
the device to typically 300 nA at 5 V and provides software-
selectable output loads while in power-down mode. The device
is put into power-down mode via the serial interface. Total
unadjusted error for the device is <1 mV.
This device exhibits very low glitch on power-up.
SYNC SCLK DIN
DACGND
Figure 1.
PRODUCT HIGHLIGHTS
1. Available in 10-lead MSOP.
2. 16-bit accurate, 1 LSB INL.
3. Low glitch on power-up.
4. High speed serial interface with clock speeds up to 30 MHz.
5. Three power-down modes available to the user.
Table 1. Related Devices
Part No.
Description
AD5061
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
4 LSBs INL, SOT-23.
AD5062
2.7 V to 5.5 V, 16-bit nanoDAC D/A,
1 LSB INL, SOT-23.
AD5040/AD5060 2.7 V to 5.5 V, 14-/16-bit nanoDAC D/A,
1 LSB INL, SOT-23.
Rev. D
Document Feedback
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responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2018 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

AD5063 Datasheet

nanoDAC

No Preview Available !

AD5063
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ............................................. 8
Terminology .................................................................................... 12
Theory of Operation ...................................................................... 13
DAC Architecture....................................................................... 13
Reference Buffer ......................................................................... 13
REVISION HISTORY
4/2018—Rev. C to Rev. D
Changed Application Section to Applications Information
Section.............................................................................................. 16
Changes to Bipolar Operation Using the AD5063 Section and
Figure 37 .......................................................................................... 16
Changes to Ordering Guide .......................................................... 18
8/2009—Rev. B to Rev. C
Changes to Features Section............................................................ 1
Changes to Output Voltage Settling Time Parameter, Table 2 ... 3
Updated Outline Dimensions ....................................................... 18
Changes to Ordering Guide .......................................................... 18
3/2006—Rev. A to Rev. B
Updated Format..................................................................Universal
Change to Features ........................................................................... 1
Change to Figure 1 ........................................................................... 1
Changes to Specifications ................................................................ 3
Change to Absolute Maximum Ratings......................................... 6
Change to Reference Buffer Section............................................. 13
Data Sheet
Serial Interface ............................................................................ 13
Input Shift Register .................................................................... 13
SYNC Interrupt .......................................................................... 13
Power-On to Midscale ............................................................... 14
Software Reset............................................................................. 14
Power-Down Modes .................................................................. 14
Microprocessor Interfacing....................................................... 14
Applications Information .............................................................. 16
Choosing a Reference for the AD5063.................................... 16
Bipolar Operation Using the AD5063 ..................................... 16
Using the AD5063 with a Galvanically Isolated Interface
Chip.............................................................................................. 17
Power Supply Bypassing and Grounding................................ 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 18
Change to Serial Interface Section ............................................... 13
Change to Table 6 ........................................................................... 14
Change to Bipolar Operation Using the AD5063 Section ........ 16
7/2005—Rev. 0 to Rev. A
Changes to Galvanically Isolated Chip Section.......................... 17
Changes to Figure 38...................................................................... 17
4/2005—Revision 0: Initial Version
Rev. D | Page 2 of 18


Part Number AD5063
Description nanoDAC
Maker Analog Devices
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AD5063 Datasheet PDF






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