AD5694R Datasheet | Analog Devices

FEATURES High relative accuracy (INL): ±2 LSB maximum at 16 bits Low drift 2.5 V reference: 2 ppm/°C typical Tiny package: 3 mm × 3 mm, 16-lead LFCSP Total unadjusted error (TUE): ±0.1% of FSR maximum Offset error: ±1.5 m V maximum Gain error: ±0.1% of FSR maximum High drive capability: 20 m A, 0.5 V from supply rails User selectable gain of 1 or 2 (GAIN pin) Reset to zero scale or midscale (RSTSEL pin) 1.8 V logic patibility Low glitch: 0.5 n V-sec 400 k Hz I2C-patible serial interface Low power: 3.3 m W at 3 V 2.7 V to 5.5 V power supply - 40°C to +105°C temperature range APPLICATIONS Optical transceivers Base-station power amplifiers Process control (PLC I/O cards) Industrial automation Data acquisition systems GENERAL DESCRIPTION The AD5696R/AD5695R/AD5694R family are low power, quad, 16-/14-/12-bit buffered voltage output DACs. The devices include a 2.5 V, 2 ppm/°C internal reference (enabled by default) and a gain select pin giving a full-scale output of 2.5 V (gain = 1) or 5 V (gain = 2). All devices operate from a single 2.7 V to 5.5 V supply, are guaranteed monotonic by design, and exhibit less than 0.1% FSR gain error and 1.5 m V offset error performance. The devices are available in a 3 mm × 3 mm LFCSP and a TSSOP package. The AD5696R/AD5695R/AD5694R also incorporate a poweron reset circuit and a RSTSEL pin that ensures that the DAC outputs power up to zero scale or midscale and remain there until a valid write takes place. Each part contains a per-channel power-down feature that reduces the current consumption of the device to 4 µA at 3 V while in power-down mode. The AD5696R/AD5695R/AD5694R use a versatile 2-wire serial interface that operates at clock rates up to 400 k Hz, and includes a VLOGIC pin intended for 1.8 V/3 V/5 V logic. FUNCTIONAL BLOCK DIAGRAM VREF INTERFACE LOGIC 10486-001 VLOGIC SCL SDA A1 A0 AD5696R/AD5695R/AD5694R 2.5V REFERENCE INPUT REGISTER STRING REGISTER DAC A INPUT REGISTER STRING REGISTER DAC B INPUT...