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Analog Devices Semiconductor Electronic Components Datasheet

AD6674 Datasheet

385 MHz BW IF Diversity Receiver

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AD6674 pdf
Data Sheet
385 MHz BW IF Diversity Receiver
AD6674
FEATURES
JESD204B (Subclass 1) coded serial digital outputs
In band SFDR = 83 dBFS at 340 MHz (750 MSPS)
In band SNR = 66.7 dBFS at 340 MHz (750 MSPS)
1.4 W total power per channel at 750 MSPS (default settings)
Noise density = −153 dBFS/Hz at 750 MSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
Flexible input range
AD6674-750 and AD6674-1000
1.46 V p-p to 1.94 V p-p (1.70 V p-p nominal)
AD6674-500
1.46 V p-p to 2.06 V p-p (2.06 V p-p nominal)
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient automatic gain control
(AGC) implementation
Noise shaping requantizer (NSR) option for main receiver
function
Variable dynamic range (VDR) option for digital
predistortion (DPD) function
2 integrated wideband digital processors per channel
12-bit numerically controlled oscillator (NCO), up to
4 cascaded half-band filters
Differential clock inputs
Integer clock divide by 1, 2, 4, or 8
Energy saving power-down modes
Flexible JESD204B lane configurations
Small signal dither
APPLICATIONS
Diversity multiband, multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, GSM, LTE, LTE-A
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
GENERAL DESCRIPTION
The AD6674 is a 385 MHz bandwidth mixed-signal
intermediate frequency (IF) receiver. It consists of two, 14-bit
1.0 GSPS/750 MSPS/500 MSPS analog-to-digital converters
(ADC) and various digital signal processing blocks consisting of
four wideband DDCs, an NSR, and VDR monitoring. It has an
on-chip buffer and a sample-and-hold circuit designed for low
power, small size, and ease of use. This product is designed to
support communications applications capable of sampling wide
bandwidth analog signals of up to 2 GHz. The AD6674 is
optimized for wide input bandwidth, high sampling rate,
excellent linearity, and low power in a small package.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
AVDD1
(1.25V)
FUNCTIONAL BLOCK DIAGRAM
AVDD2
(2.5V)
AVDD3 AVDD1_SR DVDD
(3.3V)
(1.25V)
(1.25V)
DRVDD
SPIVDD
(1.25V) (1.8V TO 3.3V)
VIN+A
VIN–A
BUFFER
FD_A
FD_B
VIN+B
VIN–B
BUFFER
ADC
SIGNAL
MONITOR
ADC
V_1P0
CLK+
CLK–
CLOCK
GENERATION
÷2
÷4
÷8
SIGNAL PROCESSING
DDDIDIGGIGIIGITTITIAATALALLLDDDODOOWOW(W(×WN(×N4(×N4×CN)4)C4O)C)CONOONVNNVEVVEREERSRRSISOSIOINOIONNN
NNOOISISEESSHHAAPPININ((×G×G22R)R)EEQQUUAANNTTIZIZEERR
VVAARRIAIABBLLEEDDYYNNAAMMICICRRAANNGGEE
((××22))
4
JESD204B
SUBCLASS 1
CONTROL
FAST
DETECT
SIGNAL
MONITOR
SPI CONTROL
AD6674
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
PDWN/
STBY
AGND
SYSREF± SYNCINB± SDIO SCLK CSB
Figure 1.
DGND DRGND
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2014 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

AD6674 Datasheet

385 MHz BW IF Diversity Receiver

No Preview Available !

AD6674 pdf
AD6674
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 3
Product Highlights ........................................................................... 4
Specifications..................................................................................... 5
DC Specifications ......................................................................... 5
AC Specifications.......................................................................... 6
Digital Specifications ................................................................... 8
Switching Specifications .............................................................. 9
Timing Specifications .................................................................. 9
Absolute Maximum Ratings.......................................................... 11
Thermal Characteristics ............................................................ 11
ESD Caution................................................................................ 11
Pin Configuration and Function Descriptions........................... 12
Typical Performance Characteristics ........................................... 14
AD6674-1000 .............................................................................. 14
AD6674-750 ................................................................................ 17
AD6674-500 ................................................................................ 20
Equivalent Circuits ......................................................................... 23
Theory of Operation ...................................................................... 25
ADC Architecture ...................................................................... 25
Analog Input Considerations.................................................... 25
Voltage Reference ....................................................................... 29
Numerically Controlled Oscillator .......................................... 43
FIR Filters ........................................................................................ 45
General Description................................................................... 45
Half-Band Filters ........................................................................ 46
DDC Gain Stage ......................................................................... 47
DDC Complex to Real Conversion ......................................... 47
DDC Example Configurations ................................................. 48
Noise Shaping Requantizer (NSR) ............................................... 52
Decimating Half-Band Filter .................................................... 52
NSR Overview ............................................................................ 52
Variable Dynamic Range (VDR) .................................................. 55
VDR Real Mode.......................................................................... 56
VDR Complex Mode ................................................................. 56
Digital Outputs ............................................................................... 58
Introduction to JESD204B Interface........................................ 58
JESD204B Overview .................................................................. 58
Functional Overview ................................................................. 59
JESD204B Link Establishment ................................................. 59
Physical Layer (Driver) Outputs .............................................. 61
JESD204B Tx Converter Mapping ........................................... 63
Configuring the JESD204B Link.............................................. 63
Multichip Synchronization............................................................ 67
SYSREF± Setup/Hold Window Monitor................................. 69
Test Modes....................................................................................... 71
ADC Test Modes ........................................................................ 71
Clock Input Considerations ...................................................... 30
Power-Down/Standby Mode..................................................... 31
Temperature Diode .................................................................... 31
ADC Overrange and Fast Detect.................................................. 32
ADC Overrange (OR)................................................................ 32
Fast Threshold Detection (FD_A and FD_B) ........................ 32
Signal Monitor ................................................................................ 33
SPORT over JESD204B.............................................................. 33
Digital Downconverter (DDC)..................................................... 36
DDC I/Q Input Selection .......................................................... 36
DDC I/Q Output Selection ....................................................... 36
DDC General Description ........................................................ 36
Frequency Translation ................................................................... 42
General Description ................................................................... 42
DDC NCO + Mixer Loss and SFDR........................................ 43
JESD204B Block Test Modes .................................................... 71
Serial Port Interface (SPI).............................................................. 74
Configuration Using the SPI..................................................... 74
Hardware Interface..................................................................... 74
SPI Accessible Features.............................................................. 74
Memory Map .................................................................................. 75
Reading the Memory Map Register Table............................... 75
Memory Map Register Table..................................................... 76
Applications Information .............................................................. 89
Power Supply Recommendations............................................. 89
Exposed Pad Thermal Heat Slug Recommendations............ 89
AVDD1_SR (Pin 57) and AGND (Pin 56, Pin 60) ................ 89
Outline Dimensions ....................................................................... 90
Ordering Guide .......................................................................... 90
Rev. A | Page 2 of 90


Part Number AD6674
Description 385 MHz BW IF Diversity Receiver
Maker Analog Devices
Total Page 30 Pages
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