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AD7546 Datasheet

CMOS 16-Bit Voltage Out DAC

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0 B${) ~lrL
~ ANALOG
W DEVICES
CMOS16-Bit
VoltageOut DAC*
I AD7546 I
FEATURES
AD7546 FUNCTIONAL BLOCK DIAGRAM
Monotonic to 16 Bits Over Temperature
On-Chip Deglitch Switch
Unipolar and Bipolar Operation
Microprocessor Compatible
TIl/CMOS Compatible latched Inputs
Voltage Output (Constant Output Impedance)
VA'"
low Cost
RI
low Power Consumption: 50mW typ
RI
OBS IIGENERAL DESCRIPTION
OThe AD7546 is a 16-bit voltage-output DAC with input data
latches for interfacing to 16-bit microprocessors. It uses a
Lnovel design consisting of a 12-bit R-2R DAC, operated in the
Evoltage switching mode, which is supplied with a reference
voltage from a 4-bit segment DAC under the control of the
TEfour most significant bits. A monolithic CMOS device. the
VOUT
AD7546 offers outstanding differential nonlinearity specifica-
R2 (35:
tions and monotonicity from 14 to 16 bits.
An on-chip deglitch switch which is synchronized with the
latch loading signal is provided for use with track/hold circuits.
VA'"
R2
so
~
SWI swa WR CS
NOTE. SWITCHES ARE SHOWN FOR SEGMENT 0
Lo" INPUT eOOE OF OXXXH.
OBIS
080
ORDERING INFORMATION
PIN CONFIGURATION
Relative
Accuracy
:to.OS%
:to.OI2%
Differential
Nonlinearity
:to.OO6%
:to.OOlS%
TemperalUre Range. Package
Plastic
0 to +70.C
Ceramic
-2S.C to +8S.C
AD7S46JN
AD7S46KN
AD7S46Ap Q
AD7S46BrJ
Monotonic
Range
14 Bits
16 Bits
MSB OB15 f2
.
PACKAGE IDENTIFICATION 1
Suffix "D": - Ceramic DIP (D40A)
Suffix UN": - Plastic DIP - (N40A)
I See Section 19 for package outline information.
AD7546
TOP VIEW
INOT TO SCALE!
A2 OUT
A2-
OBI
LSB DBO
VOUT
.Patent Pending.
-- ------


Analog Devices Semiconductor Electronic Components Datasheet

AD7546 Datasheet

CMOS 16-Bit Voltage Out DAC

No Preview Available !

SPECIFICTAIONS (VDD = +15V, VSS= -5V,
(VREF+ = +4V, VREF- = -4V, A 1, A2 = AD544K, unlessotherwisenoted)
Parameter
Limit at
TA =+2S.C
Limit at
TA = Tmin, TmaxI
Units
Conditions/Comments
ACCURACY
Resolution
All Grades
Relative Accuracy
AD7S46)N, AD
AD7S46KN, BD
Differential Nonlinearity
AD7S46)N, AD
AD7546KN, BD
Gain Error3
Positive Full Scale
Negative Full Scale
Gain T.C.4,s
16
:1:0.0S
:1:0.012
:1:0.006
:1:0.0015
-Q.02
-0.02
:1:2
16
:1:0.0S
:1:0.012
:1:0.006
:1:0.001S
-0.02
-Q.02
:1:2
Bits
% FSR m2.x2
% FSR max
% FSR max
% FSR max
% FSR max
% FSR max
ppm of FSt C max
This is an end-point linearity specification
assuming zero offset voltage for AI, A2.
=Guaranteed monotonic to 14 bits (DBO and DBI 0).
Guaranteed monotonic to 16 bits over temperature.
DAC latches loaded with FFFFH
DAC latches loaded with OOO~
de Supply Rejections
L'>Gain/L'>VDD
100 100
JlV per V typ
=VDD +14.5V to +IS.5V
DYNAMIC PERFORMANCE
Voltage Settling Times ,6
4
5
10
SWITCHING CHARACTERISTICSs ,7
toYs
tcWH
OtWR
tDS
BtDH
0
0
400
200
100
REFERENCE INPUTS
SResistance
VREF + to VREF -
ORl,R2
20/32/50
20/30/50
Rl, R2 Match
LAD7546)N, AD
AD7546 KN, BD
0.5
0.1
EVoltage Range
TVREF+
EVREF-
+5
-5
4
5
10
0
0
600
300
150
20/32/50
20/30/50
0.5
0.1
+5
-5
Jlstyp
Jlstyp
JlS typ
nsmin
ns min
nsmin
ns min
ns min
To 0.01 % of final value.
To 0.003% of final value.
To 0.00076% of final value. Measured using the
circuit of Figure 6.
With +SV input logic levels.
Chip select to WRITE setup time
Chip select to WRITE hold time
WRITE pulse width
Data setup time
Data hold time
H2, min/ryp/max
kn, minltyp/max
%max
%max
Vmax
Vmax
Typical Resistance TC is -300ppmtC
Typical TC of Rl, R2 match is :1:1ppmtC
=The AD7546 is tested with VREF +
+4V, VREF- =-4V
ANALOG OUTPUT
ROUT (Output Resistance)
COUT (Output Capacitance)s
DEGLITCH SWITCH
RON
ILEAKAGE, SW2 (pin 22)
10/15/25
8
300/600
1
10/15/25
8
450/900
10
kn, min/typ/max
pF max
n typ/max
nA max
VSW = :1:4V, Isw = 100JlA
Off switch leakage. VSWI = :1:4V,VSW2= +4V.
LOGIC INPUTS
VIH
VIL
IIN (Input Leakage Current)
CIN (Input Capacitance)s
Input Coding
POWER SUPPLY
VDD
VSS
IDD
'DD
ISS
2.4 2.4
0.8 0.8
11
88
16-Bit Unipolar Binary
16-Bit Offset Binary
+15 +15
-5 -5
44
200 200
100 100
Vmin
Vmax
JlA max
pF max
V
V
mA max
JlA max
JlA max
VlN = OV or VDD
See Figure 7
See Figure 8
:1:5%for specified performance
:1:5%for specified performance
=VIN VlL or VIH
VIN =OV or VDD, CS = WR c OV
NOTES
1Temperature ranges as follows, AD7 S46JN, KN, 0 to +70°C
AD7S46AD, BD, -25°C to +8SoC
> FSR is Full Scale Range.
s TheSj: gain error specifications have assumed an input offset voltage for A2 of OV. Actual gain error figures should include
amplifier A2 input offset voltage.
'Gain TC specifications have assumed a zero input offset voltage drift with temperature for A2. Actual gain TC figures should
include amplifier A2 drift with temperature.
. Guaranteed but not tested.
. Voltage settling time will be a function of the time constant RC seen at the buffer amplifier inputs. The resistance component of
this time constant is the equivalent output impedance of the resistor string and will vary depending on which segment is decoded.
Maximum equivalent resistance occurs at mid..cale. Worst case settling thus occurs from zero to mid-scale or from full-scale to mid-scale.
, + 15V logic can be used to reduce power dissipation but no improvement i. achieved in the timinil specifications. All control .ignals
arc ~easured with tr. tf. 20ns for +SV losic and timed from (VIH + VlL) ,Data is timed from VIH or VlL. Sample tested at
+25 C to ensure conformance.
2
Specifications subject to change without notice.
VOL. ,. 9-240 DIr./TAL- TO-ANALOG CONVERTERS
~~- - -


Part Number AD7546
Description CMOS 16-Bit Voltage Out DAC
Maker Analog Devices
Total Page 10 Pages
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