AD9207
FEATURES
- Flexible reconfigurable mon platform design
- Supports single, dual, and quad band per channel
- Datapaths and DSP blocks are fully bypassable
- On-chip PLL with multichip synchronization
- External RFCLK input option for off-chip PLL
- Support clock input frequencies up to 12 GHz
- Maximum ADC sample rate up to 6 GSPS
- Useable analog bandwidth to 8 GHz
- Maximum data rate up to 6 GSPS using JESD204C
- Noise density:
- 153 d BFS/Hz
- ADC AC performance at 6 GSPS, input at 2.7 GHz,
- 1 d BFS
- Full-scale sine wave input voltage: 1.475 V p-p
- Noise figure: 25.3 d B
- HD2:
- 70 d BFS
- HD3:
- 68 d BFS
- Worst other (excluding HD2 and HD3):
- 84 d BFS
- Versatile digital features
- Selectable decimation filters
- Configurable DDC
- 8 fine plex DDCs and 4 coarse plex DDCs
- 48-bit NCO per DDC
- Option to bypass fine and coarse DDC
- Programmable 192-tap PFIR filter for receive equalization
- Supports 4 different profile settings loaded via the GPIOx pins
- Programmable delay per datapath...
