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AD9460 - 80 MSPS/105 MSPS ADC

Description

The AD9460 is a 16-bit, monolithic, sampling, analog-to-digital converter (ADC) with an on-chip track-and-hold circuit.

It is optimized for performance, small size, and ease of use.

Features

  • 105 MSPS guaranteed sampling rate (AD9460-105) 79.4 dBFS SNR/91 dBc SFDR with 10 MHz input (3.4 V p-p input, 80 MSPS) 78.3 dBFS SNR/ with 170 MHz input (4.0 V p-p input, 80 MSPS) 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input (3.4 V p-p input, 80 MSPS) 77.2 dBFS SNR/84 dBc SFDR with 170 MHz input (3.4 V p-p input, 105 MSPS) 90 dBFS two-tone SFDR with 139 MHz/140 MHz input (3.4 V p-p input, 105 MSPS) 60 fsec rms jitter Excellent linearity DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.

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www.DataSheet4U.com 16-Bit, 80 MSPS/105 MSPS ADC AD9460 FEATURES 105 MSPS guaranteed sampling rate (AD9460-105) 79.4 dBFS SNR/91 dBc SFDR with 10 MHz input (3.4 V p-p input, 80 MSPS) 78.3 dBFS SNR/ with 170 MHz input (4.0 V p-p input, 80 MSPS) 77.8 dBFS SNR/87 dBc SFDR with 170 MHz input (3.4 V p-p input, 80 MSPS) 77.2 dBFS SNR/84 dBc SFDR with 170 MHz input (3.4 V p-p input, 105 MSPS) 90 dBFS two-tone SFDR with 139 MHz/140 MHz input (3.4 V p-p input, 105 MSPS) 60 fsec rms jitter Excellent linearity DNL = ±0.5 LSB typical INL = ±3.0 LSB typical 2.0 V p-p to 4.0 V p-p differential full-scale input Buffered analog inputs LVDS outputs (ANSI-644 compatible) or CMOS outputs Data format select (offset binary or twos complement) Output data capture clock available 3.
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