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AD9516-5 - 14-Output Clock Generator

Key Features

  • Low phase noise, phase-locked loop (PLL) External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable Six 1.6 GHz LVPECL outputs, arranged in 3 groups Each group shares a 1-to-32 divider with coarse phase delay Additive output jitter: 225 fs rms.

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Other Datasheets by Analog Devices

Part Number Description
AD9516-0 14-Output Clock Generator
AD9516-1 14-Output Clock Generator
AD9516-2 14-Output Clock Generator
AD9516-3 14-Output Clock Generator
AD9516-4 14-Output Clock Generator

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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FEATURES Low phase noise, phase-locked loop (PLL) External VCO/VCXO to 2.4 GHz optional 1 differential or 2 single-ended reference inputs Reference monitoring capability Automatic revertive and manual reference switchover/holdover modes Accepts LVPECL, LVDS, or CMOS references to 250 MHz Programmable delays in path to PFD Digital or analog lock detect, selectable Six 1.