AD9882A Datasheet | Analog Devices

FEATURES Analog interface 140 MSPS maximum conversion rate Programmable analog bandwidth 0.5 V to 1.0 V analog input range 500 ps p-p PLL clock jitter at 140 MSPS 3.3 V power supply Full sync processing Midscale clamping 4:2:2 output format mode Digital interface DVI 1.0 patible interface 112 MHz operation High skew tolerance of 1 full input clock Sync detect for hot plugging Supports high bandwidth digital content protection FUNCTIONAL BLOCK DIAGRAM ANALOG INTERFACE RAIN GAIN BAIN SOGIN HSYNC FILT VSYNC SCL SDA A0 CLAMP A/D 8 REF ROUT REFBYPASS CLAMP A/D GOUT BOUT 8 8 8 ROUT GOUT BOUT DATACK HSOUT CSOUT ROUT GOUT BOUT SOGOUT DE CLAMP A/D SYNC PROCESSING AND CLOCK GENERATION DATACK HSOUT VSOUT SOGOUT SERIAL REGISTER AND POWER MANAGEMENT DIGITAL INTERFACE RX0+ RX0- RX1+ RX1- RX2+ RX2- RXC+ RXC- RTERM DDCSCL DDCSDA MCL MDA 8 8 DVI RECEIVER 8 APPLICATIONS RGB graphics processing LCD monitors and projectors Plasma display panels Scan converter Microdisplays Digital TV DATACK DE HSYNC HDCP 05123-001 VSYNC Figure 1. GENERAL DESCRIPTION The AD9882A offers designers the flexibility of an analog interface and a digital visual interface (DVI) receiver integrated on a single chip. Also included is support for high bandwidth digital content protection (HDCP). The AD9882A also offers full sync processing for posite sync and sync-on-green (SOG) applications. Digital Interface The AD9882A contains a DVI 1.0 patible receiver and supports display resolutions up to SXGA (1280 × 1024 at 60 Hz). The receiver features an intrapair skew tolerance of up to one full clock cycle. With the inclusion of HDCP, displays can now receive encrypted video content. The AD9882A allows for authentication of a video receiver, decryption of encoded data at the receiver, and renewability of that authentication during transmission, as specified by the HDCP v1.0 protocol. It also has high tolerance of nonpliant HDCP sources. Fabricated in an advanced CMOS process, the...