ADAU1979 Datasheet - Analog Devices

Quad Analog-to-Digital Converter

ADAU1979 Features

* Four 4.5 V rms (typical) differential inputs On-chip phase-locked loop (PLL) for master clock Low electromagnetic interference (EMI) design 109 dB (typical) analog-to-digital converter (ADC) dynamic range Total harmonic distortion + noise (THD + N):

* 95 dB (typical) Selectable digital high-p

ADAU1979 General Description

The ADAU1979 incorporates four high performance, analog-to-digital converters (ADCs) with 4.5 V rms capable ac-coupled inputs. The ADCs use a multibit sigma-delta (ΣΔ) architecture with continuous time front end for low EMI. An I2C/serial peripheral interface (SPI) control port is included that allo.

ADAU1979 Datasheet (2.69 MB)