ADF41513 Datasheet | Analog Devices

FEATURES - 1 GHz to 26.5 GHz bandwidth - Ultralow noise PLL - Integer N = - 235 d Bc/Hz, fractional-N = - 231 d Bc/Hz - High maximum PFD frequency - Integer N = 250 MHz, fractional-N = 125 MHz - 25-bit fixed/49-bit variable fractional modulus mode - Single-ended reference input - 3.3 V power supply, 3.3 V charge pump - Integrated 1.8 V logic capability - Phase resync - Programmable charge pump currents: 16× range - Digital lock detect - 3-wire serial interface with register readback option - Hardware and software power-down mode - Operating range from - 40°C to +105°C APPLICATIONS - Test equipment and instrumentation - Wireless infrastructure - Microwave point to point and multipoint radios - Very small aperture terminal (VSAT) radios - Aerospace and defense FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION The ADF41513 is an ultralow noise frequency synthesizer that can be used to implement local oscillators (LOs) as high as 26.5 GHz in the upconversion and downconversion sections of wireless receivers and transmitters. The ADF41513 is designed on a high performance silicon germanium (Si Ge), bipolar plementary metal-oxide semiconductor (Bi CMOS) process, achieving a normalized phase noise floor of - 235 d Bc/Hz. The phase frequency detector (PFD) operates up to 250 MHz (integer N mode)/125 MHz (fractional-N mode) for improved phase noise and spur performance. The variable modulus, ∑-Δ modulator allows extremely fine resolution when using a 49-bit divide value. The ADF41513 can be used as an integer N phase-locked loop (PLL), or it can be used as a fractional-N PLL with either a fixed modulus for subhertz frequency resolution or variable modulus for subhertz exact frequency resolution. A plete PLL is implemented when the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). The 26.5 GHz bandwidth eliminates the need for a frequency doubler or divider stage, simplifying system architecture and reducing cost. The ADF41513 is packaged in a...