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ADF4251 Datasheet

Dual Fractional-N/Integer-N Frequency Synthesizer

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ADF4251 pdf
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Dual Fractional-N/Integer-N
Frequency Synthesizer
ADF4251
FEATURES
3.0 GHz Fractional-N/1.2 GHz Integer-N
2.7 V to 3.3 V Power Supply
Separate VP Allows Extended Tuning Voltage to 5 V
Programmable Dual Modulus Prescaler
RF: 4/5, 8/9
IF: 8/9, 16/17, 32/33, 64/65
Programmable Charge Pump Currents
3-Wire Serial Interface
Digital Lock Detect
Power-Down Mode
Programmable Modulus on Fractional-N Synthesizer
Trade-Off Noise versus Spurious Performance
Software and Hardware Power-Down
APPLICATIONS
Base Stations for Mobile Radio (GSM, PCS, DCS,
CDMA, WCDMA)
Wireless Handsets (GSM, PCS, DCS, CDMA, WCDMA,
PHS)
Wireless LANs
Communications Test Equipment
CATV Equipment
GENERAL DESCRIPTION
The ADF4251 is a dual fractional-N/integer-N frequency
synthesizer that can be used to implement local oscillators
(LO) in the upconversion and downconversion sections of
wireless receivers and transmitters. Both the RF and IF syn-
thesizers consist of a low noise digital PFD (phase frequency
detector), a precision charge pump, and a programmable refer-
ence divider. The RF synthesizer has a -based fractional
interpolator that allows programmable fractional-N division.
The IF synthesizer has programmable integer-N counters. A
complete PLL (phase-locked loop) can be implemented if the
synthesizer is used with an external loop filter and VCO (volt-
age controlled oscillator).
Control of all the on-chip registers is via a simple 3-wire inter-
face. The devices operate with a power supply ranging from
2.7 V to 3.3 V and can be powered down when not in use.
FUNCTIONAL BLOCK DIAGRAM
ADF4251
REFIN
VDD1 VDD2 VDD3 DVDD VP1
VP2
؋2
DOUBLER
4-BIT R
COUNTER
PHASE
FREQUENCY
DETECTOR
RSET
REFERENCE
CHARGE
PUMP
CE
CPRF
MUXOUT
CLK
DATA
LE
FROM
REFIN
OUTPUT
MUX
24-BIT
DATA
REGISTER
؋2
DOUBLER
LOCK
DETECT
FRACTIONAL N
RF DIVIDER
INTEGER N
IF DIVIDER
15-BIT R
COUNTER
PHASE
FREQUENCY
DETECTOR
CHARGE
PUMP
RFINA
RFINB
IFINB
IFINA
CPIF
AGND1 AGND2 DGND CPGND1 CPGND2
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.


Analog Devices Semiconductor Electronic Components Datasheet

ADF4251 Datasheet

Dual Fractional-N/Integer-N Frequency Synthesizer

No Preview Available !

ADF4251 pdf
ADF4251–SPECIFICATIONS1 (VDD1 = VDD2 = VDD3 = DVDD = 3 V ؎ 10%, VP1 = VP2 = 5 V ؎ 10%, GND = 0 V,
RSET = 2.7 k, dBm referred to 50 , TA = TMIN to TMAX, unless otherwise noted.)
Parameter
B Version
Unit
Test Conditions/Comments
RF CHARACTERISTICS
RF Input Frequency (RFINA, RFINB)2
RF Input Sensitivity
RF Input Frequency (RFINA, RFINB)2
RF Phase Detector Frequency
Allowable Prescaler Output Frequency
0.25/3.0
10/0
0.1/3.0
30
375
GHz min/max
dBm min/max
GHz min/max
MHz max
MHz max
Input Level = 8/0 dBm min/max
Guaranteed by Design
IF CHARACTERISTICS
IF Input Frequency (IFINA, IFINB)2
IF Input Sensitivity
IF Phase Detector Frequency
Allowable Prescaler Output Frequency
50/1200
10/0
55
150
MHz min/max
dBm min/max
MHz max
MHz max
Guaranteed by Design
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Sensitivity
REFIN Input Current
REFIN Input Capacitance
CHARGE PUMP
RF ICP Sink/Source
High Value
Low Value
IF ICP Sink/Source
High Value
Low Value
ICP Three-State Leakage Current
RF Sink and Source Current Matching
IF Sink and Source Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
VINH, Input High Voltage
VINL, Input Low Voltage
IINH/IINL, Input Current
CIN Input Capacitance
LOGIC OUTPUTS
VOH, Output High Voltage
VOL, Output Low Voltage
POWER SUPPLIES
VDD1, VDD2, VDD3
DVDD
VP1, VP2
IDD3
RF + IF
RF Only
IF Only
Low Power Sleep Mode/Power-Down
250
0.5/VDD1
±100
10
4.375
625
5
625
1
2
2
2
2
1.35
0.6
±1
10
VDD 0.4
0.4
2.7/3.3
VDD1
VDD1/5.5
13
10
4
10
MHz max
V p-p min/max
µA max
pF max
For f < 10 MHz, use dc-coupled square
wave (0 to VDD).
AC-coupled. When dc-coupled, use
0 to VDD max (CMOS compatible).
mA typ
µA typ
mA typ
µA typ
nA typ
% typ
% typ
% typ
% typ
V min
V max
µA max
pF max
See Table V
See Table IX
0.5 V < VCP < VP 0.5
0.5 V < VCP < VP 0.5
VCP = VP /2
V min
V max
V min/V max
V min/V max
mA typ
mA typ
mA typ
pA typ
IOH = 0.2 mA
IOL = 0.2 mA
16 mA max
13 mA max
5.5 mA max
RF NOISE AND SPURIOUS CHARACTERISTICS
Noise Floor
In-Band Phase Noise Performance4
Lowest Spur Mode
Low Noise and Spur Mode
Lowest Noise Mode
Spurious Signals
141
90
95
103
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
@ 20 MHz PFD Frequency
@ VCO Output
RFOUT = 1.8 GHz, PFD = 20 MHz
RFOUT = 1.8 GHz, PFD = 20 MHz
RFOUT = 1.8 GHz, PFD = 20 MHz
See Typical Performance Characteristics
NOTES
1Operating Temperature Range (B Version): 40°C to +85°C.
2Use a square wave for frequencies less than FMIN.
3RF = 1 GHz, RF PFD = 10 MHz, MOD = 4095, IF = 500 MHz, IF PFD = 200 kHz, REF = 10 MHz, V DD = 3 V, VP1 = 5 V, and VP2 = 3 V.
4The in-band phase noise is measured with the EVAL-ADF4251EB2 Evaluation Board and the HP5500E Phase Noise Test System. The spectrum analyzer provides the
REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). FOUT = 1.74 GHz, FREF = 20 MHz, N = 87, MOD = 100, Channel Spacing = 200 kHz, VDD = 3.3 V, and VP = 5 V.
Specifications subject to change without notice.
–2– REV. 0


Part Number ADF4251
Description Dual Fractional-N/Integer-N Frequency Synthesizer
Maker Analog Devices
Total Page 28 Pages
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