Datasheet4U Logo Datasheet4U.com

ADF4377 - Microwave Wideband Synthesizer

Datasheet Summary

Description

The ADF4377 is a high performance, ultralow jitter, dual output integer-N phased locked loop (PLL) with an integrated voltage controlled oscillator (VCO) ideally suited for data converter and mixed signal front end (MxFE) clock applications.

Features

  • Output frequency range: 800 MHz to 12.8 GHz.
  • Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz).
  • Jitter = 27 fsRMS (ADC SNR method).
  • Wideband noise floor:.
  • 160 dBc/Hz at 12 GHz.
  • PLL specifications.
  • 239 dBc/Hz: normalized in-band phase noise floor.
  • 147 dBc/Hz: normalized in-band 1/f noise.
  • Phase detector frequency up to 500 MHz.
  • Reference input frequency up to 1000 MHz.
  • Typical spurious fPFD:.
  • 95 dBc at.

📥 Download Datasheet

Datasheet preview – ADF4377

Datasheet Details

Part number ADF4377
Manufacturer Analog Devices
File Size 4.76 MB
Description Microwave Wideband Synthesizer
Datasheet download datasheet ADF4377 Datasheet
Additional preview pages of the ADF4377 datasheet.

📁 Similar Datasheet

Other Datasheets by Analog Devices
  • ADF4371 - Microwave Wideband Synthesizer
  • ADF4372 - Microwave Wideband Synthesizer
  • ADF4378 - Microwave Wideband Synthesizer
  • ADF4350 - Wideband Synthesizer
  • ADF4351 - Wideband Synthesizer
  • ADF4355 - Microwave Wideband Synthesizer
  • ADF4355-2 - Microwave Wideband Synthesizer
  • ADF4355-3 - Microwave Wideband Synthesizer

Full PDF Text Transcription

Click to expand full text
Data Sheet ADF4377 Microwave Wideband Synthesizer with Integrated VCO FEATURES ► Output frequency range: 800 MHz to 12.8 GHz ► Jitter = 18 fsRMS (integration bandwidth: 100 Hz to 100 MHz) ► Jitter = 27 fsRMS (ADC SNR method) ► Wideband noise floor: −160 dBc/Hz at 12 GHz ► PLL specifications ► −239 dBc/Hz: normalized in-band phase noise floor ► −147 dBc/Hz: normalized in-band 1/f noise ► Phase detector frequency up to 500 MHz ► Reference input frequency up to 1000 MHz ► Typical spurious fPFD: −95 dBc at fOUT = 12 GHz ► Reference input to output delay specifications ► Device-to-device standard deviation: 3 ps ► Temperature coefficient: 0.03 ps/°C ► Adjustment step size: < ±0.1 ps ► Multichip output phase alignment ► 3.
Published: |