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Analog Devices Semiconductor Electronic Components Datasheet

ADN4652 Datasheet

Dual-Channel LVDS Isolators

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Data Sheet
5 kV RMS/3.75 kV RMS, 600 Mbps,
Dual-Channel LVDS Isolators
ADN4650/ADN4651/ADN4652
FEATURES
5 kV rms/3.75 kV rms LVDS isolator
Complies with TIA/EIA-644-A LVDS standard
Multiple dual-channel configurations
Up to 600 Mbps switching with low jitter
4.5 ns maximum propagation delay
151 ps maximum peak-to-peak total jitter at 600 Mbps
100 ps maximum pulse skew
600 ps maximum part to part skew
2.5 V or 3.3 V supplies
−75 dBc power supply ripple rejection and glitch immunity
±8 kV IEC 61000-4-2 ESD protection across isolation barrier
High common-mode transient immunity: >25 kV/μs
Passes EN55022 Class B radiated emissions limits with
600 Mbps PRBS
Safety and regulatory approvals (20-lead SOIC package)
UL (pending): 5000 V rms for 1 minute per UL 1577
CSA Component Acceptance Notice 5A (pending)
VDE certificate of conformity (pending)
DIN V VDE V 0884-10 (VDE V 0884-10):2006-12
VIORM = 424 V peak
Fail-safe output high for open, short, and terminated input
conditions (ADN4651/ADN4652)
Operating temperature range: −40°C to +125°C
Choice of package and isolation options
3.75 kV rms in highly integrated 20-lead SSOP
5 kV rms in 20-lead SOIC with 7.8 mm creepage/clearance
APPLICATIONS
Analog front-end (AFE) isolation
Data plane isolation
Isolated high speed clock and data links
Isolated serial peripheral interface (SPI) over LVDS
FUNCTIONAL BLOCK DIAGRAMS
VIN1
VIN2
ADN4650 LDO ISOLATION LDO
BARRIER
VDD1
VDD2
DIN1+
DIN1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
DOUT1+
DOUT1–
DOUT2+
DOUT2–
GND1
VDD1
VIN1
ADN4651 LDO
Figure 1.
ISOLATION
BARRIER
VIN2
LDO
GND2
DIN1+
DIN1–
DOUT2+
DOUT2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DOUT1+
DOUT1–
DIN2+
DIN2–
GND1
VDD1
VIN1
ADN4652 LDO
Figure 2.
ISOLATION
BARRIER
VIN2
LDO
GND2
DOUT1+
DOUT1–
DIN2+
DIN2–
LVDS
DIGITAL ISOLATOR
LVDS
VDD2
DIN1+
DIN1–
DOUT2+
DOUT2–
GENERAL DESCRIPTION
The ADN4650/ADN4651/ADN46521 are signal isolated, low
voltage differential signaling (LVDS) buffers that operate at up
to 600 Mbps with very low jitter.
The devices integrate Analog Devices, Inc., iCoupler® technology,
enhanced for high speed operation, to provide galvanic isolation of
the TIA/EIA-644-A compliant LVDS drivers and receivers. This
technology allows drop-in isolation of an LVDS signal chain.
Multiple channel configurations are offered, and the LVDS receivers
on the ADN4651/ADN4652 include a fail-safe mechanism to
GND1
Figure 3.
GND2
ensure a Logic 1 on the corresponding LVDS driver output
when the inputs are floating, shorted, or terminated, but not driven.
For high speed operation with low jitter, the LVDS and isolator
circuits rely on a 2.5 V supply. An integrated on-chip low dropout
regulator (LDO) can provide the required 2.5 V from an external
3.3 V power supply. The devices are fully specified over a wide
industrial temperature range and are available in a 20-lead, wide
body SOIC package with 5 kV rms isolation or a 20-lead SSOP
package with 3.75 kV rms isolation.
1 Protected by U.S. Patents 5,952,849; 6,873,065; 6,903,578; and 7,075,329. Other patents are pending.
Rev. D
Document Feedback
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responsibilityisassumedbyAnalog Devicesforitsuse,norforanyinfringementsofpatentsorother
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com


Analog Devices Semiconductor Electronic Components Datasheet

ADN4652 Datasheet

Dual-Channel LVDS Isolators

No Preview Available !

ADN4650/ADN4651/ADN4652
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagrams............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Receiver Input Threshold Test Voltages .................................... 4
Timing Specifications .................................................................. 4
Insulation and Safety Related Specifications ............................ 5
Package Characteristics ............................................................... 6
Regulatory Information............................................................... 6
DIN V VDE V 0884-10 (VDE V 0884-10) Insulation
Characteristics (Pending)............................................................ 6
Recommended Operating Conditions ...................................... 7
Absolute Maximum Ratings............................................................ 8
REVISION HISTORY
1/2017—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 24
9/2016—Rev. B to Rev. C
Added 20-Lead SSOP.................................................... Throughout
Changes to Title, Features Section, and General Description .... 1
Added Table 5; Renumbered Sequentially .................................... 5
Change to Figure 5 ........................................................................... 7
Changes to PCB Layout Section ................................................... 19
Changes to Surface Tracking Section........................................... 20
Updated Outline Dimensions ....................................................... 24
Changes to Ordering Guide .......................................................... 24
4/2016—Rev. A to Rev. B
Added ADN4652 ................................................................Universal
Changes to Features Section and General Description Section ...... 1
Added Figure 3; Renumbered Sequentially .................................. 1
Changes to Supply Current Parameter, Table 1 ............................ 3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 ................................................................................................ 4
Changes to Table 12.......................................................................... 9
Moved Figure 7 ............................................................................... 10
Added Table 13................................................................................ 10
Added Figure 8 and Table 14, Renumbered Sequentially ......... 11
Changes to PCB Layout Section ................................................... 19
Changes to Ordering Guide .......................................................... 24
Data Sheet
Thermal Resistance .......................................................................8
ESD Caution...................................................................................8
Pin Configurations and Function Descriptions ............................9
Typical Performance Characteristics ........................................... 12
Test Circuits and Switching Characteristics................................ 17
Theory of Operation ...................................................................... 18
Truth Table and Fail-Safe Receiver .......................................... 18
Isolation ....................................................................................... 19
PCB Layout ................................................................................. 19
Magnetic Field Immunity.......................................................... 19
Insulation Lifetime ..................................................................... 20
Applications Information .............................................................. 22
Outline Dimensions ....................................................................... 24
Ordering Guide .......................................................................... 24
2/2016—Rev. 0 to Rev. A
Added ADN4650 ................................................................Universal
Changes to Features Section and General Description Section........1
Added Figure 1; Renumbered Sequentially ...................................1
Changes to Supply Current Parameter, Table 1 .............................3
Changes to Skew Parameter and Fail-Safe Delay Parameter,
Table 3 .................................................................................................4
Added Figure 5...................................................................................9
Changes to Table 12...........................................................................9
Changes to Figure 30 Caption and Figure 31 Caption .............. 14
Change to Figure 34 ....................................................................... 15
Changes to Truth Table and Fail-Safe Receiver Section ............ 16
Added Table 13; Renumbered Sequentially ................................ 16
Change to Applications Information Section ............................. 20
Added Figure 41 ............................................................................. 20
Changes to Ordering Guide .......................................................... 22
11/2015—Revision 0: Initial Version
Rev. D | Page 2 of 25


Part Number ADN4652
Description Dual-Channel LVDS Isolators
Maker Analog Devices
Total Page 25 Pages
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