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ADSP-21566 - High Performance DSP

General Description

3 SHARC Processor 4 SHARC+ Core Architecture 6 System Infrastructure 8 System Memory Map 8 Security

Key Features

  • Enhanced SHARC+ high performance floating-point core Up to 1 GHz Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS compliant 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant Low system power across automotive tempe.

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Other Datasheets by Analog Devices

Part Number Description
ADSP-21560 SHARC+ Single Core High Performance DSP
ADSP-21561 SHARC+ Single Core High Performance DSP
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ADSP-21567 High Performance DSP
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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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SHARC+ Single Core High Performance DSP (Up to 1 GHz) SYSTEM FEATURES Enhanced SHARC+ high performance floating-point core Up to 1 GHz Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed Powerful DMA system On-chip memory protection Integrated safety features 17 mm × 17 mm, 400-ball CSP_BGA (0.8 mm pitch), RoHS compliant 120-lead LQFP_EP (0.4 mm pitch), RoHS compliant Low system power across automotive temperature range ADSP-21566/21567/21569 MEMORY Large on-chip Level 2 (L2) SRAM with ECC protection, up to 1 MB One Level 3 (L3) interface optimized for low system power, providing 16-bit interface to DDR3 (supporting 1.