Description
3
ARM Cortex-A5 Processor (ADSP-SC592/SC594 Only) 5
SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security
Features
- Dual-enhanced SHARC+ floating-point cores High performance SHARC+ cores (up to 1 GHz each) Up to 5 Mb (640 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed-point support Byte, short word, word, and long word addressability
Arm Cortex-A5 core Up to 1 GHz/1600 DMIPS with NEON/VFPv4-D16 32 kB L1 instruction and data caches with parity 256 kB L2 cache with parity
Powerful DMA system with 8 MemDMAs On-chip.
ADSP-21593-AnalogDevices.pdf
