ADSP-BF539F Datasheet | Analog Devices

FEATURES Preliminary Technical Data 1.0 V to 1.2 V core VDD with on-chip voltage regulation 3.3 V tolerant I/O with specific 5 V tolerant pins 316-ball Pb-free mini-BGA package Up to 500 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and piler friendly support Advanced debug, trace, and performance monitoring Blackfin® Embedded Processor ADSP-BF539/ADSP-BF539F External memory controller with glueless support for SDRAM, SRAM, flash, and ROM Flexible memory booting options from SPI®, external memory PERIPHERALS Parallel peripheral interface (PPI), supporting ITU-R 656 video data formats Four dual-channel, full-duplex synchronous serial ports, supporting 16 stereo I2S® channels Two DMA controllers supporting 26 channels Controller area network (CAN) 2.0B controller Media transceiver (MXVR) for connection to a MOST® network Three SPI-patible ports Three timer/counters with PWM support Three UARTs with support for Ir DA® Two TWI controllers patible with I2C® industry standard 38 general purpose I/O pins (GPIO) 16 general purpose flag pins (GPF) Real time clock Watchdog timer Debug/JTAG interface On-chip PLL capable of 0.5x To 64x frequency multiplication JTAG TEST AND EMULATION MEMORY 148K bytes of on-chip memory: 16K bytes of instruction SRAM/cache 64K bytes of instruction SRAM 32K bytes of data SRAM 32K bytes of data SRAM/cache 4K bytes of scratchpad SRAM 512K x 16-bits or 256K x 16-bits of flash memory (ADSP-BF539F only) Four dual-channel memory DMA controllers Memory management unit providing memory protection VOLTAGE REGULATOR PERIPHERAL ACCESS BUS TWI0-1 CAN 2.0B DM A CO RE BUS 3 GPIO PORT C DMA ACCESS BUS 1 INTERRUPT CONTROLLER PERIPHERAL ACCESS BUS WATCHDOG TIMER RTC PPI MXVR SPI1-2 DMA ACCESS BUS 0 GPIO PORT D DMA CONTROLLER1 L1 INSTRUCTION MEMORY L1 DATA MEMORY DMA CONTROLLER0 TIMER0-2 SPI0 UART0 SPORT0-1 UART1-...