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ADSP-BF548 - Embedded Processor

Download the ADSP-BF548 datasheet PDF. This datasheet also covers the ADSP-BF542 variant, as both devices belong to the same embedded processor family and are provided as variant models within a single manufacturer datasheet.

Description

3 Low Power Architecture 4 System Integration 4 Blackfin Processor Peripherals 4 Blackfin Processor Core 4 Memory Architecture 6 DMA Controllers 9 Real-Time Clock 10 Watchdog Timer 10 Timers 10 Up/Down Counter and Thumbwheel Interface 11 Serial Ports (SPORTs) 11 Serial Peripheral Interfa

Features

  • Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs RISC-like register and instruction model Wide range of operating voltages and flexible booting options Programmable on-chip voltage regulator 400-ball CSP_BGA, RoHS compliant package MEMORY Up to 324K bytes of on-chip memory comprised of instruction SRAM/cache; dedicated instruction SRAM; data SRAM/cache; dedicated data SRAM; scratchpad SRAM External sync memory controller supporting either.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADSP-BF542_AnalogDevices.pdf) that lists specifications for multiple related part numbers.

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Other Datasheets by Analog Devices

Part Number Description
ADSP-BF542 Embedded Processor
ADSP-BF544 Embedded Processor
ADSP-BF547 Blackfin Embedded Processor
ADSP-BF549 Embedded Processor
ADSP-BF504 Blackfin Embedded Processor

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
Blackfin Embedded Processor ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549 FEATURES Up to 600 MHz high performance Blackfin processor Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs RISC-like register and instruction model Wide range of operating voltages and flexible booting options Programmable on-chip voltage regulator 400-ball CSP_BGA, RoHS compliant package MEMORY Up to 324K bytes of on-chip memory comprised of instruction SRAM/cache; dedicated instruction SRAM; data SRAM/cache; dedicated data SRAM; scratchpad SRAM External sync memory controller supporting either DDR SDRAM or mobile DDR SDRAM External async memory controller supporting 8-/16-bit async memories and burst flash devices NAND flash controller 4 memory-to-memory DMA pairs, 2 with ext.
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