Up to 240 MHz ARM Cortex-M4 with floating-point unit with up to 160K Byte zero-wait-state ECC SRAM Safety based dual independent- core concept Up to 1M Byte high performa.

......... 3 Analog Front End ......... 4 Dual-Core System Architecture 10 EmbeddedICE .. 13 Processor Infrastructure ......... 13 Memory Architecture .. 17 System Acceleration .... 19 Security Features ........ 19 Security Features Disclaimer .... 1.

ADSP-CM411F

ADSP-CM412F

ADSP-CM413F

ADSP-CM416F

ADSP-CM417F

ADSP-CM418F

ADSP-CM402F

ADSP-CM403F

ADSP-CM407F

ADSP-CM408F

ADSP-CM409F

ADSP-1010A

ADSP-2100A