ADSP-SC570 - SHARC+ Dual-Core DSP

Analog Devices

Datasheet Details

3 ARM Cortex-A5 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security

Dual-enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 3 Mb (384 kB) L1 SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short word, word, long word addressed ARM Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache with parity/32 kB L1 data cache with parity 256 kB L2 cache with parity Powerful DMA system On-chip memory pr.

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Published: Jul 26, 2016 |