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HMC988LP3E Datasheet PROGRAMMABLE CLOCK DIVIDER/DELAY

Manufacturer: Analog Devices

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General Description

The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32.

It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option.

Housed in a compact 3x3 mm SMT QFN package, the clock divider offers a high level of functionality.

Overview

Clock Distribution - SMT HMC988LP3E v04.1014 PROGRAMMABLE CLOCK DIVIDER AND DELAY DC - 4 GHz Typical Applications The HMC988LP3E is ideal for: • Basestation Digital Pre-Distortion Paths(DPD) • High Performance Automated.

Key Features

  • DC - 4 GHz -170 dBc/Hz floor @ 100 MHz output -164 dBc/Hz floor @ 2 GHz output Integrated Jitter 35 fsRMS@ 100 MHz output 13 fsRMS(calculated) @ 2 GHz output Adjustable output phase with soft/hard reset sync Adjustable output delay in 60 steps of 20 ps Flexible Input Interface: LVPECL,LVDS,CML,CMOS Compatible AC or DC Coupling On - Chip Termination 50 Ω (100 Ω Differential) Output Driver (LVPECL): 800 mVpp LVPECL into 50 Ω Single-Ended (+3 dBm Fo) Up to 8 addressable dividers per SPI bus 3.3 V o.

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